11.1 Device-Specific Information

Table 11-1. PORTA Availability
Device	Bit Field	Bit 15/7	Bit 14/6	Bit 13/5	Bit 12/4	Bit 11/3	Bit 10/2	Bit 9/1	Bit 8/0
64-Pin	15:8					✔	✔	✔	✔
64-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
48-Pin	15:8							✔	✔
48-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
36-Pin	15:8
36-Pin	7:0	✔			✔	✔	✔	✔	✔

Table 11-2. PORTB Availability
Device	Bit Field	Bit 15/7	Bit 14/6	Bit 13/5	Bit 12/4	Bit 11/3	Bit 10/2	Bit 9/1	Bit 8/0
64-Pin	15:8			✔	✔	✔	✔	✔	✔
64-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
48-Pin	15:8
48-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
36-Pin	15:8
36-Pin	7:0		✔		✔	✔	✔	✔	✔

Table 11-3. PORTC Availability
Device	Bit Field	Bit 15/7	Bit 14/6	Bit 13/5	Bit 12/4	Bit 11/3	Bit 10/2	Bit 9/1	Bit 8/0
64-Pin	15:8					✔	✔	✔	✔
64-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
48-Pin	15:8
48-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
36-Pin	15:8
36-Pin	7:0			✔	✔		✔	✔	✔

Table 11-4. PORTD Availability
Device	Bit Field	Bit 15/7	Bit 14/6	Bit 13/5	Bit 12/4	Bit 11/3	Bit 10/2	Bit 9/1	Bit 8/0
64-Pin	15:8								✔
64-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
48-Pin	15:8							✔	✔
48-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
36-Pin	15:8
36-Pin	7:0				✔	✔	✔	✔	✔

Table 11-5. ANSELA Availability
Name	Bit Field	Bit 15/7	Bit 14/6	Bit 13/5	Bit 12/4	Bit 11/3	Bit 10/2	Bit 9/1	Bit 8/0
64-Pin	15:8					✔	✔	✔	✔
64-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
48-Pin	15:8							✔	✔
48-Pin	7:0	✔			✔	✔	✔	✔	✔
36-Pin	15:8
36-Pin	7:0	✔			✔	✔	✔	✔	✔

Table 11-6. ANSELB Availability
Name	Bit Field	Bit 15/7	Bit 14/6	Bit 13/5	Bit 12/4	Bit 11/3	Bit 10/2	Bit 9/1	Bit 8/0
64-Pin	15:8					✔	✔	✔	✔
64-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
48-Pin	15:8							✔	✔
48-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
36-Pin	15:8
36-Pin	7:0		✔		✔	✔	✔	✔	✔

Table 11-7. ANSELC Availability
Name	Bit Field	Bit 15/7	Bit 14/6
64-Pin	15:8
64-Pin	7:0	✔	✔
48-Pin	15:8
48-Pin	7:0	✔	✔
36-Pin	15:8
36-Pin	7:0

Table 11-8. ANSELD Availability
Name	Bit Field	Bit 14/6	Bit 13/5
64-Pin	15:8
64-Pin	7:0	✔	✔
48-Pin	15:8
48-Pin	7:0	✔
36-Pin	15:8
36-Pin	7:0

Table 11-9. PPS Availability by Package
64-Pin	48-Pin	36-Pin
RP1-RP12	RP1-RP10	RP1-RP12
RP17-RP30	RP17-RP26	RP17-RP30
RP33-RP44	RP33-RP40	RP33-RP44
RP49-RP57	RP49-RP52	RP49-RP57
	RP55

Table 11-10. Selectable Input Sources (Maps Input to Function)
Input Name⁽¹⁾	Function Name	Register	Register Bitfield
External Interrupt 1	INT1	RPINR0	INT1R[7:0]
External Interrupt 2	INT2	RPINR0	INT2R[7:0]
External Interrupt 3	INT3	RPINR0	INT3R[7:0]
External Interrupt 4	INT4	RPINR1	INT4R[7:0]
Timer1 External Clock	T1CK	RPINR1	T1CKR[7:0]
Timer2 External Clock	T2CK	RPINR1	T2CKR[7:0]
Timer3 External Clock	T3CK	RPINR1	T3CKR[7:0]
SCCP Input Clock 1	TCKI1	RPINR2	TCKI1R[7:0]
SCCP Input Capture 1	ICM1	RPINR2	ICM1R[7:0]
SCCP Input Clock 2	TCKI2	RPINR2	TCKI2R[7:0]
SCCP Input Capture 2	ICM2	RPINR2	ICM2R[7:0]
SCCP Input Clock 3	TCKI3	RPINR3	TCKI3R[7:0]
SCCP Input Capture 3	ICM3	RPINR3	ICM3R[7:0]
SCCP Input Clock 4	TCKI4	RPINR3	TCKI4R[7:0]
SCCP Input Capture 4	ICM4	RPINR3	ICM4R[7:0]
SCCP Input Clock 5	TCKI5	RPINR4	TCKI5R[7:0]
SCCP Input Capture 5	ICM5	RPINR4	ICM5R[7:0]
Reserved
SCCP Fault A	OCFA	RPINR7	OCFAR[7:0]
SCCP Fault B	OCFB	RPINR7	OCFBR[7:0]
SCCP Fault C	OCFC	RPINR7	OCFCR[7:0]
SCCP Fault D	OCFD	RPINR7	OCFDR[7:0]
PWM Input 8	PCI8	RPINR8	PCI8R[7:0]
PWM Input 9	PCI9	RPINR8	PCI9R[7:0]
PWM Input 10	PCI10	RPINR8	PCI10R[7:0]
PWM Input 11	PCI11	RPINR8	PCI11R[7:0]
QEI1 Input A	QEIA1	RPINR9	QEIA1R[7:0]
QEI1 Input B	QEIB1	RPINR9	QEIB1R[7:0]
QEI1 Index Input	QEINDX1	RPINR9	QEINDX1R[7:0]
QEI1 Home Input	QEIHOME1	RPINR9	QEIHOM1R[7:0]
UART1 Receive	U1RX	RPINR13	U1RXR[7:0]
UART1 Data-Set-Ready	U1DSR	RPINR13	U1DSRR[7:0]
UART2 Receive	U2RX	RPINR13	U2RXR[7:0]
UART2 Data-Set-Ready	U2DSR	RPINR13	U2DSRR[7:0]
UART3 Receive	U3RX	RPINR14	U3RXR[7:0]
UART3 Data-Set-Ready	U3DSR	RPINR14	U3DSRR[7:0]
SPI1 Data Input	SDI1	RPINR14	SDI1R[7:0]
SPI1 Clock Input	SCK1IN	RPINR14	SCK1R[7:0]
SPI1 Client Select	SS1IN	RPINR15	SS1R[7:0]
SPI2 Data Input	SDI2	RPINR15	SDI2R[7:0]
SPI2 Clock Input	SCK2IN	RPINR15	SCK2R[7:0]
SPI2 Client Select	SS2IN	RPINR15	SS2R[7:0]
SPI3 Data Input	SDI3	RPINR16	SDI3R[7:0]
SPI3 Clock Input	SCK3IN	RPINR16	SCK3R[7:0]
SPI3 Client Select	SS3IN	RPINR16	SS3R[7:0]
CAN 1 Receive	CAN1RX	RPINR17	CAN1RXR[7:0]
SENT 1 Input	SENT1	RPINR18	SENT1R[7:0]
SENT 2 Input	SENT2	RPINR18	SENT2R[7:0]
Reference Clock 1 Input	REFI1	RPINR18	REFI1R[7:0]
Reference Clock 2 Input	REFI2	RPINR18	REFI2R[7:0]
PWM PCI Input 12	PCI12	RPINR19	PCI12R[7:0]
PWM PCI Input 13	PCI13	RPINR19	PCI13R[7:0]
PWM PCI Input 14	PCI14	RPINR19	PCI14R[7:0]
PWM PCI Input 15	PCI15	RPINR19	PCI15R[7:0]
PWM PCI Input 16	PCI16	RPINR20	PCI16R[7:0]
PWM PCI Input 17	PCI17	RPINR20	PCI17R[7:0]
PWM PCI Input 18	PCI18	RPINR20	PCI18R[7:0]
CLC Input A	CLCINA	RPINR20	CLCAR[7:0]
CLC Input B	CLCINB	RPINR21	CLCBR[7:0]
CLC Input C	CLCINC	RPINR21	CLCCR[7:0]
CLC Input D	CLCIND	RPINR21	CLCDR[7:0]
CLC Input E	CLCINE	RPINR21	CLCER[7:0]
CLC Input F	CLCINF	RPINR22	CLCFR[7:0]
CLC Input G	CLCING	RPINR22	CLCGR[7:0]
CLC Input H	CLCINH	RPINR22	CLCHR[7:0]
CLC Input I	CLCINI	RPINR22	CLCIR[7:0]
CLC Input J	CLCINJ	RPINR23	CLCJR[7:0]
ADC Trigger 31 Input	ADTRG31	RPINR23	ADTRG31R[7:0]
UART1 Clear to Send	U1CTS	RPINR23	U1CTSR[7:0]
UART2 Clear to Send	U2CTS	RPINR23	U2CTSR[7:0]
UART3 Clear to Send	U3CTS	RPINR24	U3CTSR[7:0]
BiSS Return Input	BISS1SL	RPINR24	BISS1SLR[7:0]
BiSS Get Sense Input	BISS1GS	RPINR24	BISS1GSR[7:0]
IOMONITOR1 Feedback 12	IOMON1F12	RPINR24	IOIM0R[7:0]
IOMONITOR1 Feedback 13	IOMON1F13	RPINR25	IOIM1R[7:0]
IOMONITOR1 Feedback 14	IOMON1F14	RPINR25	IOIM2R[7:0]
IOMONITOR1 Feedback 15	IOMON1F15	RPINR25	IOIM3R[7:0]
PWM Input 19	PCI19	RPINR26	PCI19R[7:0]
PWM Input 20	PCI20	RPINR27	PCI20R[7:0]
PWM Input 21	PCI21	RPINR27	PCI21R[7:0]
PWM Input 22	PCI22	RPINR27	PCI22R[7:0]
UART4 Receive	U4DS	RPINR28	U4DSR[7:0]
UART4 Data-Set-Ready	U4RX	RPINR28	U4DSR[7:0]
UART4 Clear to Send	U4CTS	RPINR28	U4CTSR[7:0]
Note: Unless otherwise noted, all inputs use the Schmitt Trigger input buffers.

Table 11-11. Pin Correlation to Input Remap #⁽¹⁾
Index	Source Signal	Remap Input #
181	RPV15	PI181
180	RPV14	PI180
179	RPV13	PI179
178	RPV12	PI178
177	RPV11	PI177
176	RPV10	PI176
175	RPV9	PI175
174	RPV8	PI174
173	RPV7	PI173
172	RPV6	PI172
171	RPV5	PI171
170	RPV4	PI170
169	RPV3	PI169
168	RPV2	PI168
167	RPV1	PI167
166	RPV0	PI166
165	Touch TX8	PI165
164	Touch TX9	PI164
163	Touch TX10	PI163
162	Touch TX11	PI162
161	Touch TX12	PI161
160	Touch TX13	PI160
159	Touch TX14	PI159
158	Touch TX15	PI158
157-152	Reserved	PI157-PI152
151	PWM Off Request - DAC5	PI151
150	PWM On Request - DAC5	PI150
149	PWM Off Request - DAC4	PI149
148	PWM On Request - DAC4	PI148
147	PWM Off Request - DAC3	PI147
146	PWM On Request - DAC3	PI146
145	PWM Off Request - DAC2	PI145
144	PWM On Request - DAC2	PI144
143	PWM Off Request - DAC1	PI143
142	PWM On Request - DAC1	PI142
141	Reserved	PI141
140	PWM Event Out 2	PI140
139	PWM Event Out 1	PI139
138	PTG TRIG[27]	PI138
137	PTG TRIG[26]	PI137
136-134	Reserved	Reserved
133	CMP5	PI133
132	CMP4	PI132
131	CMP3	PI131
130	CMP2	PI130
129	CMP1	PI129
128-58	Reserved	Reserved
57	RD8	RPI57
56	RD7	RPI56
55	RD6	RPI55
54	RD5	RPI54
53	RD4	RPI53
52	RD3	RPI52
51	RD2	RPI51
50	RD1	RPI50
49	RD0	RPI49
48-45	Reserved	RPI48-RPI145
44	RC11	RPI44
43	RC10	RPI43
42	RC9	RPI42
41	RC8	RPI41
40	RC7	RPI40
39	RC6	RPI39
38	RC5	RPI38
37	RC4	RPI37
36	RC3	RPI36
35	RC2	RPI35
34	RC1	RPI34
33	RC0	RPI33
32-31	Reserved	RPI32-RPI31
30	RB13	RPI30
29	RB12	RPI29
28	RB11	RPI28
27	RB10	RPI27
26	RB9	RPI26
25	RB8	RPI25
24	RB7	RPI24
23	RB6	RPI23
22	RB5	RPI22
21	RB4	RPI21
20	RB3	RPI20
19	RB2	RPI19
18	RB1	RPI18
17	RB0	RPI17
16-13	Reserved	RPI16-RPI13
12	RA11	RPI12
11	RA10	RPI11
10	RA9	RPI10
9	RA8	RPI9
8	RA7	RPI8
7	RA6	RPI7
6	RA5	RPI6
5	RA4	RPI5
4	RA3	RPI4
3	RA2	RPI3
2	RA1	RPI2
1	RA0	RPI1
Note: This list of output signals can be mapped to any of the peripheral inputs listed in Table 11-10.

Table 11-12. Virtual Outputs to Remappable Ouput Registers⁽¹⁾
Virtual Outputs	Remappable Output Register	Register Bitfield
RPV0	RPOR32	RP128R[6:0]
RPV1	RPOR32	RP129R[6:0]
RPV2	RPOR32	RP130R[6:0]
RPV3	RPOR32	RP131R[6:0]
RPV4	RPOR33	RP132R[6:0]
RPV5	RPOR33	RP133R[6:0]
RPV6	RPOR33	RP134R[6:0]
RPV7	RPOR33	RP135R[6:0]
RPV8	RPOR34	RP136R[6:0]
RPV9	RPOR34	RP137R[6:0]
RPV10	RPOR34	RP138R[6:0]
RPV11	RPOR34	RP139R[6:0]
RPV12	RPOR35	RP140R[6:0]
RPV13	RPOR35	RP141R[6:0]
RPV14	RPOR35	RP142R[6:0]
RPV15	RPOR35	RP143R[6:0]
Note: This list of virtual output signals can be mapped to any of the peripheral inputs listed in Table 11-10.

Table 11-13. Output Selection for Remappable Pins (RPn)
Function	RPnR[5:0]	Output Name
PWM1H	1	RPn tied to PWM1H Output
PWM1L	2	RPn tied to PWM1L Output
PWM2H	3	RPn tied to PWM2H Output
PWM2L	4	RPn tied to PWM2L Output
PWM3H	5	RPn tied to PWM3H Output
PWM3L	6	RPn tied to PWM3L Output
PWM4H	7	RPn tied to PWM4H Output
PWM4L	8	RPn tied to PWM4L Output
CAN1TX	9	RPn tied to CAN1 Output
U1TX	10	RPn tied to UART1 Transmit
U1RTS	11	RPn tied to UART1 Request-to-Send
U2TX	12	RPn tied to UART2 Transmit
U2RTS	13	RPn tied to UART2 Request-to-Send
U3TX	14	RPn tied to UART3 Transmit
U3RTS	15	RPn tied to UART3 Request-to-Send
U4TX	16	RPn tied to UART4 Transmit
U4RTS	17	RPn tied to UART4 Request-to-Send
SDO1	18	RPn tied to SPI1 Data Output
SCK1	19	RPn tied to SPI1 Clock Output
SS1	20	RPn tied to SPI1 Client Select
SDO2	21	RPn tied to SPI2 Data Output
SCK2	22	RPn tied to SPI2 Clock Output
SS2	23	RPn tied to SPI2 Client Select
SDO3	24	RPn tied to SPI3 Data Output
SCK3	25	RPn tied to SPI3 Clock Output
SS3	26	RPn tied to SPI3 Client Select
REFO1	27	RPn tied to Reference Clock 1 Output
REFO2	28	RPn tied to Reference Clock 2 Output
OCM1	29	RPn tied to SCCP1 Output
OCM2	30	RPn tied to SCCP2 Output
OCM3	31	RPn tied to SCCP3 Output
OCM4	32	RPn tied to SCCP4 Output
MCCP5A	33	RPn tied to MCCP5 Output A
MCCP5B	34	RPn tied to MCCP5 Output B
MCCP5C	35	RPn tied to MCCP5 Output C
MCCP5D	36	RPn tied to MCCP5 Output D
MCCP5E	37	RPn tied to MCCP5 Output E
MCCP5F	38	RPn tied to MCCP5 Output F
CMP1	39	RPn tied to Comparator 1 Output
CMP2	40	RPn tied to Comparator 2 Output
CMP3	41	RPn tied to Comparator 3 Output
CMP4	42	RPn tied to Comparator 4 Output
CMP5	43	RPn tied to Comparator 5 Output
PEVTA	44	RPn tied to PWM Event A Output
PEVTB	45	RPn tied to PWM Event B Output
PEVTC	46	RPn tied to PWM Event C Output
PEVTD	47	RPn tied to PWM Event D Output
PWME	48	RPn tied to PWM Event E Output
PWMF	49	RPn tied to PWM Event F Output
QEICMP1	50	RPn tied to QEI1 Comparator Output
CLC1OUT	51	RPn tied to CLC1 Output
CLC2OUT	52	RPn tied to CLC2 Output
CLC3OUT	53	RPn tied to CLC3 Output
CLC4OUT	54	RPn tied to CLC4 Output
PTGTRG24	55	RPn tied to PTG Trigger 24 Output
PTGTRG25	56	RPn tied to PTG Trigger 25 Output
SENT1OUT	57	RPn tied to SENT1 Output
SENT2OUT	58	RPn tied to SENT2 Output
BISSMO1	59	RPn tied to BiSS Line Digital Output 1 Enable
BISSMA1	60	RPn tied to BiSS Line Digital Clock 1
U1DTRn	61	RPn tied to UART1 Data Terminal Ready Output
U2DTRn	62	RPn tied to UART2 Data Terminal Ready Output
U3DTRn	63	RPn tied to UART3 Data Terminal Ready Output
U4DTRn	64	RPn tied to UART4 Data Terminal Ready Output
RDCEXC	65	RPn tied to RDC Excitation Output
RDCEXCI	66	RPn tied to RDC Excitation Inverted Output
PTGTRG18	67	RPn tied to PTG Trigger 18 Output
PTGTRG19	68	RPn tied to PTG Trigger 19 Output
PTGTRG20	69	RPn tied to PTG Trigger 20 Output

Table 11-14. IOIM 1-8 Group A Reference Pins
REFSEL	Pin Function Name	Pin
`0111`	IOMAD7	RC2
`0110`	IOMAD6	RC5
`0101`	IOMAD5	RC3
`0100`	IOMAD4	RC4
`0011`	IOMAD3	RD0
`0010`	IOMAD2	RD1
`0001`	IOMAD1	RD2
`0000`	IOMAD0	RD3

Table 11-15. IOIM 1-8 Group A Feedback Pins
FBKSEL	Pin Function Name	Pad
`0111`	IOMAF7	RC7
`0110`	IOMAF6	RC1
`0101`	IOMAF5	RC0
`0100`	IOMAF4	RD7
`0011`	IOMAF3	RD8
`0010`	IOMAF2	RA0
`0001`	IOMAF1	RA7
`0000`	IOMAF0	RB7