21.3.6 UARTx Timing Parameter A Register

Note:
  1. The WIP bit is relevant when the UART clock differs from the CPU clock. It indicates whether the UART and CPU clocks are synchronized for writes to the parameter registers.
  2. To write to P2 without affecting P1, use UxPAbits.P2 = value. Writing to the entire UxPA register overwrites P1, potentially causing unexpected behavior in LIN and Address Detect modes. When accessing through pointers, ensure a 16-bit pointer targets P2's base address for writing.
Name: UxPA
Offset: 0x1714, 0x1754, 0x1794, 0x17D4

Bit 3130292827262524 
 WIP      P2[8] 
Access R/WR/W 
Reset 0 
Bit 2322212019181716 
 P2[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset  
Bit 15141312111098 
        P1[8] 
Access R/W 
Reset 0 
Bit 76543210 
 P1[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bit 31 – WIP  UxPA Write in Progress bit(1)

ValueDescription
1 Write is still in progress (the user should not update the UxPA register).
0 No write in progress (user can update the UxPA register).

Bits 24:16 – P2[8:0]  Parameter 2 bits(2)

DMX RX:

The First Byte Number to Receive – 1, not including the start code (bits[8:0]).

LIN Responder TX:

Number of bytes to transmit (bits [7:0]).

Asynchronous RX with Address Detect:

ADDR to match (bits[7:0]).

Smart Card Mode:

Block Time Counter (BTC) bits. This counter is operated on the bit clock, whose period is always equal to one ETU (bits[8:0]).

Other Modes:

Not used.

Bits 8:0 – P1[8:0] Parameter 1 bits

DMX TX:

Number of bytes to transmit – 1 (not including the start code).

LIN Commander TX:

PID to transmit (bits[5:0]).

Asynchronous TX with Address Detect:

Address to transmit. A ‘1’ is automatically inserted into bit 9 (bits [7:0]).

Smart Card Mode:

Guard Time Counter bits. This counter operates on the bit clock, whose period is always equal to one ETU (bits[8:0]).

Other Modes:

Not used.