20.3.1 QEI 1 Control Register

Note:

When CCMx = 10 or CCMx = 11, all of the QEI counters operate as timers and the PIMOD[2:0] bits are ignored.
When CCMx = 00, and QEAx and QEBx values match the Index Match Value (IMV), the POSxCNT registers are reset.
The selected clock rate should be at least twice the expected maximum quadrature count rate.
The index match value applies to the A&B inputs after the SWAP, and polarity bits have been applied.
The QCAPEN and HCAPEN bits must be cleared during PIMODx modes two through seven to ensure proper functionality.
This bit operational only for CCM[1:0] mode “00”.
A zero value in HMATCH[2:0] will not start the delay counter operation.
Polarity bit applied for External Trigger input.
QEI coherent capture event cannot trigger itself.
Hall sensor redefines the operation of all of the QEI inputs; the home pin functions are not applicable for Hall sensor. The INDEX pin is used as QEC input for Hall state derivation.
For Hall Sensor mode, it is not recommended to use any of the position counter modes that utilize index signals. Only PIMOD[2:0] = "000" or "110" are recommended; mode "101" may be used, but in general this mode is not relevant to Hall sensor applications.
By default, QEI operates in quadrature count mode when HALLEN = 0

Name:	QEI1CON
Offset:	0x1A00


Bit	31	30	29	28	27	26	25	24
	HALLEN	HPDLYEN	HMATCHEN	HMATCH[28:26]			ECAPPOL	HLDRD
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	HLDWR	HCRE	ECAPEN[21:16]
Access	R/W	R/W	R/W	R/W	R/W
Reset	0	1	0	0	0


Bit	15	14	13	12	11	10	9	8
	QEIEN		QEISIDL	PIMOD[2:0]			IMV[1:0]
Access	R/W		R/W	R/W	R/W	R/W	R/W	R/W
Reset	0		0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
		INTDIV[2:0]			CNTPOL	GATEN	CCM[1:0]
Access		R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset		0	0	0	0	0	0	0

Bit 31 – HALLEN Hall Sensor Mode Enable bit⁽⁶⁾

Value	Description
`1`	Hall mode is enabled.
`0`	QEI mode is enabled.

Bit 30 – HPDLYEN Hall Programmable Delay Function Enable bit⁽⁷⁾

Value	Description
`1`	Programmable event generation delay after a Hall transition is enabled.
`0`	Programmable event generation delay after a Hall transition is disabled.

Bit 29 – HMATCHEN Hall Filter Match Function Enable bit

Value	Description
`1`	Hall Filter match state function is enabled.
`0`	Hall Filter match state function is disabled.

Bits 28:26 – HMATCH[28:26] Hall Filter Match bits

The HMATCH register bits are used to generate an interrupt if the filter output state matches the HMATCH[2:0] value.

Bit 25 – ECAPPOL Position Counter Capture Polarity Select bit⁽⁸⁾

Value	Description
`1`	Input is inverted.
`0`	Input is not inverted.

Bit 24 – HLDRD Hold READ Coherent Transfer Select bit

Value	Description
`1`	Triggers a coherent transfer from POSCNT to POSHLD and IDXCNT to IDXHLD.
`0`	Does not trigger coherent transfer from POSCNT to POSHLD and IDXCNT to IDXHLD.

Bit 23 – HLDWR Hold Write Coherent Transfer Select bit

Value	Description
`1`	Triggers a coherent transfer from POSHLD to POSCNT and IDXHLD to IDXCNT.
`0`	Does not trigger a coherent transfer from POSHLD to POSCNT and IDXHLD to IDXCNT.

Bit 22 – HCRE Hardware Coherent Read Transfer Enable bit

Value	Description
`1`	Hardware Coherent read transfer is enabled when External Capture Rise Interrupt occurs.
`0`	Hardware Coherent read transfer is disabled.

Bits 21:19 – ECAPEN[21:16] External Trigger Encoder Count Registers Capture Select bits

Value	Description
11111	ADTRG31(PPS)
11110	ADTRG30(PPS)
11100	ADC2 End of conversion
11011	ADC1 End of conversion
11010	QEI2 coherent read capture event⁽⁹⁾
11001	QEI1 coherent read capture event⁽⁹⁾
11000	CLC2 Output
10111	CLC1 Output
10110	MCCP9 trigger output
10101	SCCP4 trigger output
10100	SCCP3 trigger output
10011	SCCP2 trigger output
10010	SCCP1 trigger output
10001	PWM8 ADC trigger 1
10000	PWM8 ADC trigger 0
01111	PWM7 ADC trigger 1
01110	PWM7 ADC trigger 0
01101	PWM6 ADC trigger 1
01100	PWM6 ADC trigger 0
01011	PWM5 ADC trigger 1
01010	PWM5 ADC trigger 0
01001	PWM4 ADC trigger 1
01000	PWM4 ADC trigger 0
00111	Reserved
00110	PWM3 ADC trigger 1
00101	PWM3 ADC trigger 0
00100	PWM2 ADC trigger 1
00011	PWM2 ADC trigger 0
00010	PWM1 ADC trigger 1
00001	PWM1 ADC trigger 0
00000	No Counter capture function with external trigger input

Bit 15 – QEIEN Quadrature Encoder Interface Module Counter Enable bit

Value	Description
`1`	Module counters are enabled.
`0`	Module counters are disabled, but SFRs can be read or written.

Bit 13 – QEISIDL QEI Stop in Idle Mode bit

Value	Description
`1`	Discontinues module operation when device enters Idle mode.
`0`	Continues module operation in Idle mode.

Bits 12:10 – PIMOD[2:0] Position Counter Initialization Mode Select bits^(1,5,10,11)

Value	Description
`111`	Modulo Count mode for position counter and every index event loads the position counter with QEIxLEC register.
`110`	Modulo Count mode for position counter.
`101`	Resets the position counter when the position counter equals the QEIxGEC register.
`100`	Second index event after home event initializes the position counter with the contents of the QEIxINIT register.
`011`	First index event after home event initializes the position counter with the contents of the QEIxINIT register.
`010`	Next index input event initializes the position counter with the contents of the QEIxINIT register.
`001`	Every index input event resets the position counter.
`000`	Index input event does not affect the position counter.

Bits 9:8 – IMV[1:0] Index Match Value bits^(2,4)

Value	Description
`11`	Index match occurs when QEBx = `1` and QEAx = `1`.
`10`	Index match occurs when QEBx = `1` and QEAx = `0`.
`01`	Index match occurs when QEBx = `0` and QEAx = `1`.
`00`	Index match occurs when QEBx = `0` and QEAx = `0`.

Bits 6:4 – INTDIV[2:0] Timer Input Clock Prescale Select bits⁽³⁾

(Interval timer, main timer (position counter), velocity counter and index counter internal clock divider select)

Value	Description
`111`	1:128 prescale value
`110`	1:64 prescale value
`101`	1:32 prescale value
`100`	1:16 prescale value
`011`	1:8 prescale value
`010`	1:4 prescale value
`001`	1:2 prescale value
`000`	1:1 prescale value

Bit 3 – CNTPOL Position and Index Counter/Timer Direction Select bit

Value	Description
`1`	Counter direction is negative unless modified by an external up/down signal.
`0`	Counter direction is positive unless modified by an external up/down signal.

Bit 2 – GATEN External Count Gate Enable bit

Value	Description
`1`	External gate signal controls position counter operation.
`0`	External gate signal does not affect position counter operation.

Bits 1:0 – CCM[1:0] Counter Control Mode Selection bits⁽¹²⁾

Value	Description
`11`	Internal Timer mode
`10`	External Clock Count with External Gate mode
`01`	External Clock Count with External Up/Down mode
`00`	Quadrature/Hall Sensor Count mode