20.3.3 QEI 1 Status Register
Note:
- This status bit is only applicable
to PIMOD[2:0] modes, ‘
011’ and ‘100’. - Outside of Hall mode, this bit is always read '
0'. - This bit can be used in both Hall mode and Encoder mode.
- This bit operational only for Hall mode.
Legend: C = Clearable bit; HS = Hardware Settable bit
| Name: | QEI1STAT |
| Offset: | 0x1A08 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| ECAPIRQ | ECAPIEN | HPLDYIRQ | HPLDYIEN | ||||||
| Access | R/W/HS | R/W/HS | R/W/HS | R/W/HS | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| HSTAMIRQ | HSTAMIEN | HSTACIRQ | HSTACIEN | HSERRIRQ | HSERRIEN | TERRIRQ | TERRIEN | ||
| Access | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DIRIRQ | DIRIEN | PCHEQIRQ | PCHEQIEN | PCLEQIRQ | PCLEQIEN | POSOVIRQ | POSOVIEN | ||
| Access | R/W/HS | R/W/HS | R/W/HS | R/W | R/W/HS | R/W | R/W/HS | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PCIIRQ | PCIIEN | VELOVIRQ | VELOVIEN | HOMIRQ | HOMIEN | IDXIRQ | IDXIEN | ||
| Access | R/W/HS | R/W | R/W/HS | R/W | R/W/HS | R/W | R/W/HS | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 27 – ECAPIRQ External Capture Rise Interrupt Status bit(3)
| Value | Description |
|---|---|
1 |
External Capture Rise Interrupt was generated. |
0 |
No External Capture Rise Interrupt was generated. |
Bit 26 – ECAPIEN External Capture Rise Interrupt Enable bit(3)
| Value | Description |
|---|---|
1 |
External Capture Rise interrupt is enabled. |
0 |
External Capture Rise interrupt is disabled. |
Bit 25 – HPLDYIRQ Hall Programmable Delay Interrupt Status bit(2)
| Value | Description |
|---|---|
1 |
Hall programmable delay interrupt was generated. |
0 |
Hall programmable delay interrupt was not generated. |
Bit 24 – HPLDYIEN Hall Programmable Delay Interrupt Enable bit(2)
| Value | Description |
|---|---|
1 |
Hall programmable delay interrupt is enabled. |
0 |
Hall programmable delay interrupt is disabled. |
Bit 23 – HSTAMIRQ Hall state match interrupt Status bit(2)
| Value | Description |
|---|---|
1 |
Hall state match interrupt was generated. |
0 |
Hall state match interrupt was not generated. |
Bit 22 – HSTAMIEN Hall State Match Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Hall state match interrupt is enabled. |
0 |
Hall state match interrupt is disabled. |
Bit 21 – HSTACIRQ Hall State Change Interrupt Status bit(2)
| Value | Description |
|---|---|
1 |
Hall state change interrupt was generated. |
0 |
Hall state change interrupt was not generated. |
Bit 20 – HSTACIEN Hall State Change Interrupt Enable bit(4)
| Value | Description |
|---|---|
1 |
Hall state change interrupt is enabled. |
0 |
Hall state change interrupt is disabled. |
Bit 19 – HSERRIRQ Hall State Error interrupt Status bit(2)
| Value | Description |
|---|---|
1 |
Hall State Error interrupt was generated. |
0 |
Hall State Error interrupt was not generated. |
Bit 18 – HSERRIEN Hall State Error Interrupt Enable bit(4)
| Value | Description |
|---|---|
1 |
Hall State Error Interrupt is enabled. |
0 |
Hall State Error Interrupt is disabled. |
Bit 17 – TERRIRQ Quadrature/Hall Transition Error interrupt Status bit(4)
| Value | Description |
|---|---|
1 |
Quadrature/Hall Transition Error interrupt was generated. |
0 |
Quadrature/Hall Transition Error interrupt was not generated. |
Bit 16 – TERRIEN Quadrature/Hall Transition Error Interrupt Enable bit(4)
| Value | Description |
|---|---|
1 |
Quadrature/Hall Transition Error interrupt is enabled. |
0 |
Quadrature/Hall Transition Error interrupt is disabled. |
Bit 15 – DIRIRQ Direction Change Interrupt Status bit
| Value | Description |
|---|---|
1 |
Direction change interrupt was generated. |
0 |
Direction change interrupt was not generated. |
Bit 14 – DIRIEN Direction change Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Direction change Interrupt is enabled. |
0 |
Direction change Interrupt is disabled. |
Bit 13 – PCHEQIRQ Position Counter Greater Than Compare Status bit
| Value | Description |
|---|---|
1 |
POSxCNT > QEIxGEC |
0 |
POSxCNT < QEIxGEC |
Bit 12 – PCHEQIEN Position Counter Greater Than Compare Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Position Counter Greater Than Compare Interrupt is enabled. |
0 |
Position Counter Greater Than Compare Interrupt is disabled. |
Bit 11 – PCLEQIRQ Position Counter Less Than Compare Status bit
| Value | Description |
|---|---|
1 |
POSxCNT < QEIxLEC |
0 |
POSxCNT > QEIxLEC |
Bit 10 – PCLEQIEN Position Counter Less Than Compare Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Position Counter Less Than Compare Interrupt is enabled. |
0 |
Position Counter Less Than Compare Interrupt is disabled. |
Bit 9 – POSOVIRQ Position Counter Overflow Status bit
| Value | Description |
|---|---|
1 |
Position Counter Overflow has occurred. |
0 |
Position Counter Overflow has not occurred. |
Bit 8 – POSOVIEN Position Counter Overflow Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Position Counter Overflow Interrupt is enabled. |
0 |
Position Counter Overflow Interrupt is disabled. |
Bit 7 – PCIIRQ Position Counter (Homing) Initialization Process Complete Status bit(1)
| Value | Description |
|---|---|
1 |
POSxCNT was reinitialized. |
0 |
POSxCNT was not reinitialized. |
Bit 6 – PCIIEN Position Counter (Homing) Initialization Process Complete Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Position Counter (Homing) Initialization Process Complete Interrupt is enabled. |
0 |
Position Counter (Homing) Initialization Process Complete Interrupt is disabled. |
Bit 5 – VELOVIRQ Velocity Counter Overflow Status bit
| Value | Description |
|---|---|
1 |
Velocity Counter Overflow has occurred. |
0 |
Velocity Counter Overflow has not occurred. |
Bit 4 – VELOVIEN Velocity Counter Overflow Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Velocity Counter Overflow Interrupt is enabled. |
0 |
Velocity Counter Overflow Interrupt is disabled. |
Bit 3 – HOMIRQ Home Event Status bit
| Value | Description |
|---|---|
1 |
Home event has occurred. |
0 |
No home event has occurred. |
Bit 2 – HOMIEN Home Input Event Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Home Input Event Interrupt is enabled. |
0 |
Home Input Event Interrupt is disabled. |
Bit 1 – IDXIRQ Index Event Status bit
| Value | Description |
|---|---|
1 |
Index event has occurred. |
0 |
No index event has occurred. |
Bit 0 – IDXIEN Index Input Event Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Index Input Event Interrupt is enabled. |
0 |
Index Input Event Interrupt is disabled. |