3.4.5.2 Instruction Cache Parity

Parity calculation and error detection on a chosen Instruction Cache line are shown in Figure 3-26. This error detection scheme assumes that address tag data, valid bits, and LRU status are implemented in registers. Therefore, error detection is provided on the RAM elements of the Instruction Cache only.

For a cache line to have integrity, the valid bit must be set, and the parity check must pass. If a bit error occurs in the cache memory causing a parity error, recovery is made by invalidating the cache line associated with the error. The cache line can simply be re-fetched from program memory, resulting in additional latency caused by the new fetch.

In the event of a cache hit and an integrity error, an interrupt event is signaled to the CPU, the cache line is invalidated, and a re-fetch is initiated from Flash memory using the appropriate ISB buffer slice according to the LRU algorithm.