24.4.2 Bus Configuration

The I³C module supports three types of I³C bus configurations, as defined by the MIPI I³C Specification:

Pure Bus: The configuration with only I³C devices present on the bus.
Mixed Fast Bus: The configuration with both I³C devices and Legacy I²C Targets present on the bus. In this case, the legacy I²C Targets are restricted to those that are generally permissible (i.e., Target-only, no clock stretching, and have a true I²C 50 ns glitch filter on SCL).
Mixed Slow/Limited Bus: The configuration with both I³C devices and legacy I²C Targets present on the bus. In this case, the legacy I²C Targets are restricted to those that are selectively backward compatible with the I²C standard (i.e., Target-only and no clock stretching). However, these do not have a true I²C 50 ns glitch filter on SCL.

In a mixed bus configuration, the maximum possible data rate with I³C devices depends on the compliance of the I²C Target as defined by the I²C specification. The maximum data rate as specified in the I³C specification is possible only if all I²C Targets have the 50 ns spike filter.

In the absence of spike filters or if the presence of a filter is unknown, the maximum data rate is limited to only FM or FM+, even for I³C devices (as per the I³C Specification). I²C Targets are not allowed to extend the clock.