24.4.7 SRAM Error Correcting Code (ECC)

The module is capable of correcting one-bit errors and detecting two-bit errors in the SRAM read data stream.

Each 32-bit RAM word has corresponding ECC parity bits for single-bit error correction (SEC) and double-bit error detection (DED). Any single-bit error across the 32 bits of data or 7 parity bits in a RAM word is corrected on reads. Any two-bit errors in a RAM word are detected. More than two-bit errors in a single RAM word may not be correctly classified as an uncorrectable DED error.

Once read, the SRAM contents are examined in real-time. If a single-bit error is detected, the module automatically corrects the bit error on the read data bus while capturing the ECC value, and it invokes an interrupt to the CPU (IFSx[I3CxSEIF]). This informs the user to take the appropriate course of action for the given event. If the error is dual-bit, the same (uncorrected) data is presented as output and invokes an interrupt to the CPU (IFSx[I3CxDEIF]). This informs the user to take the appropriate course of action for the given event.

During write operations, ECC parity bits are automatically calculated and written for each 32-bit RAM word.