4.3.1 Bus Initiator Priority Control Register
Note:
- CPU has the highest priority.
| Name: | BMXINITPR |
| Offset: | 0x770 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| NVMPR | CAN1PR | CRYPTPR | DMAPR | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 3 – NVMPR NVM Priority Override bit
| Value | Description |
|---|---|
1 |
Raise NVM initiator RAM access priority above CPU. |
0 |
No change to NVM initiator RAM access priority. |
Bit 2 – CAN1PR CAN1 Priority Override bit
| Value | Description |
|---|---|
1 |
Raise CAN 1 initiator priority above CPU. |
0 |
No change to CAN 1 initiator priority. |
Bit 1 – CRYPTPR Crypto Priority Override bit
| Value | Description |
|---|---|
1 |
Raise Crypto Accelerator priority above CPU. |
0 |
No change to Crypto Accelerator priority. |
Bit 0 – DMAPR DMA Priority Override bit
| Value | Description |
|---|---|
1 |
Raise DMA initiator RAM access above CPU. |
0 |
No change to DMA initiator RAM access priority. |