24.7.1 Sleep in Controller Mode Operation

When a device enters Sleep mode, the system clock used by the core processor and peripherals is halted.

If I3CxCON[SLPEN] = 1, the module will continue to request the I³C peripheral clock when the device enters Sleep mode.

If I3CxCON[SLPEN] = 0, the module will discontinue requesting the I³C peripheral clock when the device enters Sleep mode.

The SCL clock generator stops when the I3CxCON[SLPEN] = 0 because the I³C peripheral clock stops. If the I³C peripheral clock stops in the middle of a transaction, then the transmission/reception stops in place, and stopping the clock in the middle of the data communication will result in undefined behavior on the I³C bus. It is highly recommended that you enter sleep mode to complete data communication with acknowledgment.

Upon exit from sleep, the clocks start up, the clock generator continues where it left off, and SCL resumes. Any in-progress transaction may continue, as the module still thinks that it is in the middle of a transaction and waits for more data. Hence, the following transaction is usually missed. However, the module snaps back as soon as it sees a stop on the bus. A Stop or a Restart on the bus means the transaction has ended, so the module can recover by itself.

There is no automatic way to prevent sleep entry if a transmission or reception is pending. The user software must synchronize sleep entry with I³C operation to avoid aborted transmissions. It is highly recommended to restart the I³C communication after exiting Sleep mode.

If the module clocks are suspended in Sleep mode while having Controller mode active, the module will most likely need to be re-enabled to synchronize it back up with the I³C bus activity.