12.3.8 PLL Divider Register

Name:	PLLxDIV
Offset:	0x319C, 0x31A8


Bit	31	30	29	28	27	26	25	24
					PLLPRE[3:0]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	1


Bit	23	22	21	20	19	18	17	16
								PLLFBDIV[8]
Access								R/W
Reset								0


Bit	15	14	13	12	11	10	9	8
	PLLFBDIV[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	1	1	0	0	1	0	0	0


Bit	7	6	5	4	3	2	1	0
			POSTDIV1[2:0]			POSTDIV2[2:0]
Access			R/W	R/W	R/W	R/W	R/W	R/W
Reset			1	0	0	0	1	0

Bits 27:24 – PLLPRE[3:0] PLLx Reference Clock Prescale bits

The allowable PLL reference input clock frequency is 5 MHz to 800 MHz.

Value	Description
1111	15x divide
1110	14x divide
...
0010	2x divide
0001	1x divide
0000	Undefined, not allowed

Bits 16:8 – PLLFBDIV[8:0] PLLx Feedback Divider bits

The allowable PLL reference input clock frequency is 5 MHz to 800 MHz.

Value	Description
101000000	320x divide
100111111	319x divide
...
000000010	2x divide
000000001	1x divide
000000000	Undefined, not allowed

Bits 5:3 – POSTDIV1[2:0] PLLx Post Divider #1 bits

Value	Description
111	7x divide
110	6x divide
...
010	2x divide
001	1x divide
000	Undefined, not allowed

Bits 2:0 – POSTDIV2[2:0] PLLx Post Divider #2 bits

Value	Description
111	7x divide
110	6x divide
...
010	2x divide
001	1x divide
000	Undefined, not allowed

DS70005629C

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.