12.3.10 User Clock Diagnostics Control Register
| Name: | CLKDIAG |
| Offset: | 0x31B4 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| FLTIJEN | STOPPLL2 | STOPPLL1 | GENSEL[4:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| SCSFLTDATA[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| STOPGEN16 | STOPGEN15 | STOPGEN14 | STOPGEN13 | STOPGEN12 | STOPGEN11 | STOPGEN10 | STOPGEN9 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| STOPGEN8 | STOPGEN7 | STOPGEN6 | STOPGEN5 | STOPGEN4 | STOPGEN3 | STOPGEN2 | STOPGEN1 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 31 – FLTIJEN SCS[x][3:0]Fault Injection Enable bit
| Value | Description |
|---|---|
| 1 | Fault is inserted. |
| 0 | Fault insertion is disabled. |
Bit 30 – STOPPLL2 PLL2 Reference Clock Monitor Disable bit
| Value | Description |
|---|---|
| 1 | Selected reference clock for PLL2 is disconnected from the associated clock monitor. |
| 0 | Selected reference clock for PLL2 is connected to the associated clock monitor. |
Bit 29 – STOPPLL1 PLL1 Reference Clock Monitor Disable bit
| Value | Description |
|---|---|
| 1 | Selected reference clock for PLL1 is disconnected from the associated clock monitor. |
| 0 | Selected reference clock for PLL1 is connected to the associated clock monitor. |
Bits 28:24 – GENSEL[4:0] Select the Clock Generator or PLL Generator for Fault Injection bits
| Value | Description |
|---|---|
| 11111 | Reserved for future PLL generators |
| 11110 | PLLGEN2 |
| 11101 | PLLGEN1 |
| 11100-10000 | Reserved for future clock generators |
| 01111 | CLKGEN16 |
| 01110 | CLKGEN15 |
| 01101 | CLKGEN14 |
| 01100 | CLKGEN13 |
| 01011 | CLKGEN12 |
| 01010 | CLKGEN11 |
| 01001 | CLKGEN10 |
| 01000 | CLKGEN9 |
| 00111 | CLKGEN8 |
| 00110 | CLKGEN7 |
| 00101 | CLKGEN6 |
| 00100 | CLKGEN5 |
| 00011 | CLKGEN4 |
| 00010 | CLKGEN3 |
| 00001 | CLKGEN2 |
| 00000 | CLKGEN1 |
Bits 19:16 – SCSFLTDATA[3:0] Fault Data to be Injected bits
Ones invert the SCS[x] data bit.
Zeros do not effect the SCS[x] data.
Bit 15 – STOPGEN16 Stops the selected reference clock to the clock monitor for CLKGEN16 bit
| Value | Description |
|---|---|
| 1 | Selected reference clock for CLKGEN16 is disconnected from the associated clock monitor. |
| 0 | Selected reference clock for CLKGEN16 is connected to the associated clock monitor. |
Bit 14 – STOPGEN15 Stops the selected reference clock to the clock monitor for CLKGEN15 bit
| Value | Description |
|---|---|
| 1 | Selected reference clock for CLKGEN15 is disconnected from the associated clock monitor. |
| 0 | Selected reference clock for CLKGEN15 is connected to the associated clock monitor. |
Bit 13 – STOPGEN14 Stops the selected reference clock to the clock monitor for CLKGEN14 bit
| Value | Description |
|---|---|
| 1 | Selected reference clock for CLKGEN14 is disconnected from the associated clock monitor. |
| 0 | Selected reference clock for CLKGEN14 is connected to the associated clock monitor. |
Bit 12 – STOPGEN13 Stops the selected reference clock to the clock monitor for CLKGEN13 bit
| Value | Description |
|---|---|
| 1 | Selected reference clock for CLKGEN13 is disconnected from the associated clock monitor. |
| 0 | Selected reference clock for CLKGEN13 is connected to the associated clock monitor. |
Bit 11 – STOPGEN12 Stops the selected reference clock to the clock monitor for CLKGEN12 bit
| Value | Description |
|---|---|
| 1 | Selected reference clock for CLKGEN12 is disconnected from the associated clock monitor. |
| 0 | Selected reference clock for CLKGEN12 is connected to the associated clock monitor. |
Bit 10 – STOPGEN11 Stops the selected reference clock to the clock monitor for CLKGEN11 bit
| Value | Description |
|---|---|
| 1 | Selected reference clock for CLKGEN11 is disconnected from the associated clock monitor. |
| 0 | Selected reference clock for CLKGEN11 is connected to the associated clock monitor. |
Bit 9 – STOPGEN10 Stops the selected reference clock to the clock monitor for CLKGEN10 bit
| Value | Description |
|---|---|
| 1 | Selected reference clock for CLKGEN10 is disconnected from the associated clock monitor. |
| 0 | Selected reference clock for CLKGEN10 is connected to the associated clock monitor. |
Bit 8 – STOPGEN9 Stops the selected reference clock to the clock monitor for CLKGEN9 bit
| Value | Description |
|---|---|
| 1 | Selected reference clock for CLKGEN9 is disconnected from the associated clock monitor. |
| 0 | Selected reference clock for CLKGEN9 is connected to the associated clock monitor. |
Bit 7 – STOPGEN8 Stops the selected reference clock to the clock monitor for CLKGEN8 bit
| Value | Description |
|---|---|
| 1 | Selected reference clock for CLKGEN8 is disconnected from the associated clock monitor. |
| 0 | Selected reference clock for CLKGEN8 is connected to the associated clock monitor. |
Bit 6 – STOPGEN7 Stops the selected reference clock to the clock monitor for CLKGEN7 bit
| Value | Description |
|---|---|
| 1 | Selected reference clock for CLKGEN7 is disconnected from the associated clock monitor. |
| 0 | Selected reference clock for CLKGEN7 is connected to the associated clock monitor. |
Bit 5 – STOPGEN6 Stops the selected reference clock to the clock monitor for CLKGEN6 bit
| Value | Description |
|---|---|
| 1 | Selected reference clock for CLKGEN6 is disconnected from the associated clock monitor. |
| 0 | Selected reference clock for CLKGEN6 is connected to the associated clock monitor. |
Bit 4 – STOPGEN5 Stops the selected reference clock to the clock monitor for CLKGEN5 bit
| Value | Description |
|---|---|
| 1 | Selected reference clock for CLKGEN5 is disconnected from the associated clock monitor. |
| 0 | Selected reference clock for CLKGEN5 is connected to the associated clock monitor. |
Bit 3 – STOPGEN4 Stops the selected reference clock to the clock monitor for CLKGEN4 bit
| Value | Description |
|---|---|
| 1 | Selected reference clock for CLKGEN4 is disconnected from the associated clock monitor. |
| 0 | Selected reference clock for CLKGEN4 is connected to the associated clock monitor. |
Bit 2 – STOPGEN3 Stops the selected reference clock to the clock monitor for CLKGEN3 bit
| Value | Description |
|---|---|
| 1 | Selected reference clock for CLKGEN3 is disconnected from the associated clock monitor. |
| 0 | Selected reference clock for CLKGEN3 is connected to the associated clock monitor. |
Bit 1 – STOPGEN2 Stops the selected reference clock to the clock monitor for CLKGEN2 bit
| Value | Description |
|---|---|
| 1 | Selected reference clock for CLKGEN2 is disconnected from the associated clock monitor. |
| 0 | Selected reference clock for CLKGEN2 is connected to the associated clock monitor. |
Bit 0 – STOPGEN1 Stops the selected reference clock to the clock monitor for CLKGEN1 bit
| Value | Description |
|---|---|
| 1 | Selected reference clock for CLKGEN1 is disconnected from the associated clock monitor. |
| 0 | Selected reference clock for CLKGEN1 is connected to the associated clock monitor. |