12.3.11 Clock Monitor Control Register

Name:	CMxCON
Offset:	0x3200, 0x3230, 0x3260, 0x3290


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
	ON		SIDL	SLPEN
Access	R/W		R/W	R/W
Reset	0		0	0


Bit	7	6	5	4	3	2	1	0
			CNTDIV[1:0]		FLTINJ[1:0]			WIDTH
Access			R/W	R/W	R/W	R/W		R/W
Reset			0	0	0	0		0

Bit 15 – ON Clock Monitor Enable bit

Value	Description
1	Clock Monitor is enabled.
0	Clock Monitor is disabled.

Bit 13 – SIDL Stop in Idle bit

Value	Description
1	Clock Monitor block will stop when IDLE mode is entered.
0	Clock Monitor block will continue to operate when IDLE mode is entered.

Bit 12 – SLPEN Sleep Mode Enable bit

Value	Description
1	Module continues to operate in Sleep modes.
0	Module does not operate in Sleep modes.

Bits 5:4 – CNTDIV[1:0] Counter Divider bits

Value	Description
11	Reserved
10	Divide-by 4
01	Divide-by 2
00	Divide-by 1

Bits 3:2 – FLTINJ[1:0] Fault Injection Sequence Enable bits

Please refer to the Fault Injection section for more details.

Value	Description
`11`	Artificial catastrophic fault injected
`10`	High frequency drift fault injected
`01`	Low frequency drift fault injected
`00`	Fault injection sequence disabled

Bit 0 – WIDTH Time Window Selection Control bit

This control bit selects whether the Time Window Generator’s clock high pulse defines the accumulation time window period.

Value	Description
1	Rising Edge to Next Falling Edge
0	Rising Edge to Rising Edge, see WINPR[31:0]

DS70005629C

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