The individual bytes in this
multibyte register can be accessed with the following register names:
CxBDIAG0T: Accesses the top byte BDIAG0[31:24]
CxBDIAG0U: Accesses the upper byte BDIAG0[23:16]
CxBDIAG0: Accesses the byte BDIAG0[31:0]
The register bits keep track
of bus errors during the nominal and data bit rate phases separately, which
helps to determine whether errors occur during the arbitration or data
transmission phase.
These counters are always incremented by 1
for any bus error.
Name:
C1BDIAG0
Offset:
0x2638
Bit
31
30
29
28
27
26
25
24
DTERRCNT[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
DRERRCNT[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
NTERRCNT[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
NRERRCNT[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bits 31:24 – DTERRCNT[7:0] Data Bit Rate
Transmit Error Counter bits
Bits 23:16 – DRERRCNT[7:0] Data Bit Rate
Receive Error Counter bits
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
