2.3.1.3 Global Pins
The following table lists the global pins.
| Name | Type | Description |
|---|---|---|
| HCLKA/B/C/D | Dedicated (hardwired) clocks A, B, C, and D | These pins are the clock inputs for sequential modules or north PLLs. Input levels are compatible with all supported I/O standards. There is a P/N pin pair for support of differential I/O standards. Single-ended clock I/Os can only be assigned to the P side of a paired I/O. This input is directly wired to each R-cell and offers clock speeds independent of the number of R-cells being driven. When the HCLK pins are unused, it is recommended that they are tied to ground. |
| CLKE/F/G/H | Routed clocks E, F, G, and H | These pins are clock inputs for clock distribution networks or south PLLs. Input levels are compatible with all supported I/O standards. There is a P/N pin pair for support of differential I/O standards. Single-ended clock I/Os can only be assigned to the P side of a paired I/O. The clock input is buffered prior to clocking the R-cells. When the CLK pins are unused, Microchip recommends to tie the CLK pins to the ground. |