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10.1 Features
-
2 x 8-Bit, High-Performance AVR RISC CPUs and Interrupt Controllers Operating in Dual-Core Lockstep
Mode
- 135 Instructions
- Hardware Multiplier
- Dual-Core Lockstep Support is Implemented by:
- Internal Observation Points and Stack Limit Check Hardware
- Duplicated CPU Interrupt Controller (CPUINT)
- Dual, Redundant Comparators Verifying the Dual CPU Cores (Lockstep)
- Data Bus Parity Check on Read Memory Data
- Fault Injection in Comparators
- 32 8-Bit Registers Directly Connected to the ALU
- Stack in RAM
- Stack Pointer Limit Check
- Data Bus Parity Check
- Illegal Opcode Check
- Stack Pointer Accessible in I/O Memory Space
- Direct Addressing of up to 64 KB of Memory
- Efficient Support for 8-, 16-, and 32-Bit Arithmetic
- Configuration Change Protection for System-Critical Features
- Native On-Chip Debugging (OCD) Support:
- Two Hardware Breakpoints
- Change of Flow, Interrupt, and Software Breakpoints
- Run-Time Read-Out of Stack Pointer (SP) Register, Program Counter (PC), and Status
Register (SREG)
- Register File Read- and Writable in Stopped Mode