30.2 Overview

The primary function of the Synchronous Watchdog Timer (SWDT) is to generate an interrupt or notify the Error Controller in the event of a software malfunction, potentially issuing a system reset. The SWDT has a 24-bit counter that counts down when the SWDT is enabled. Two different count modes are selectable using the MODE bit in the Control A (CTRLA) register:
  • MODE=0 (CLOCK): The SWDT counts clock cycles, decrementing the counter by one for every clock cycle until the count reaches zero. This mode is similar to a high-frequency synchronous WDT.
  • MODE=1 (INSTRUCTION): The SWDT counts instructions, decrementing the counter by one whenever an instruction is completed until the count reaches zero. Instructions are not fetched when the processor is in sleep mode. This mode is helpful for ensuring exact control over the execution time of specific loops and system activities. This mode is also useful in systems with multiple bus hosts that compete for bus resources, possibly preventing the CPU from using the bus 100%, which would cause cycle inaccuracy in program execution. The number of CPU instructions between two points in the code would still be deterministic.

The 24-bit counter can be read by software at any time to verify that it works. Although the counter is only 24 bits, the register for reading it (CNT) is 32 bits (with the upper byte fixed at zero) for straightforward use with 32-bit data types. Because there is no mechanism to simultaneously read all four bytes, the individual bytes of the counter will be read at slightly different times and will be inconsistent. This poses no problem, however, for verifying that the counter is changing.

An SWDT expiration (EXP) error occurs if the counter reaches zero, which is considered a software error. The software must periodically reset the SWDT counter by writing a sequence of commands to the COMMAND register to prevent this from happening. The correct sequence of commands will load the counter with the value in the Reset Value register. Like the counter, the Reset Value is only 24 bits, but it is accessed via a 32-bit RESET register (with the upper byte fixed at zero) for straightforward use with 32-bit data types.

The SWDT is used in safety-critical applications where software functionality and sequencing failure must be detected. The main benefit of using the SWDT instead of the WDT is that the SWDT runs on CLK_PER, making it much easier to configure a tight window because measuring the expected number of counts between SWDT resets can be done with high accuracy. In contrast, the WDT is clocked independently of and asynchronously to the CPU. The WDT requires a broad window due to synchronization jitter and the wide frequency tolerance of the WDT clock source.

The SWDT cannot work when the system is asleep or the main clock has stopped, unlike the WDT. The SWDT is thus a supplement to the WDT, not a replacement.