11.3.3.2 Bus Error From Bus Target

The bus target will return a bus error to the bus initiator if the initiator requests a bus transfer to or from a reserved address in the bus target address space or if any of the already mentioned checks fail.

A target may return bus error in additional, target-specific ways. Refer to the target’s documentation for information on specific bus error triggers. Examples of triggers leading to a bus error response can be:

Reading from a write-only register
Writing to a read-only register
Writing outside of a Configuration Change Protection (CCP) writing sequence to a register under CCP
Accessing a 16-bit register in the wrong sequence

A target that detects a bus error will normally discard the access as follows:

A write will not update any Special Function Registers (SFR), memories, or any other state in the target
A read will cause the target to output an undefined value on the data bus, along with the target error signal

For more information on how various targets handle bus errors, refer to the section on that specific target.