19.4.2.5 Arbitration
If a DMA channel is enabled and not suspended when it receives a transfer trigger, it will send a transfer request to the arbiter. When the arbiter receives the transfer request, it will include the DMA channel in the queue of channels with pending transfers, and the corresponding Pending Channel n bit in the Pending Channels (PENDCH.PENDCHn) registers will be set. Depending on the arbitration scheme, the arbiter will choose which DMA channel will be the next active channel. The active channel is the DMA channel granted access to perform its next beat transfer. When the arbiter has granted a DMA channel access to the DMAC, the corresponding PENDCH.PENDCHn bit will be cleared. See also Figure 19-4.
If the upcoming beat transfer is the first for the transfer request, the corresponding Busy Channel n bit in the Busy Channels register will be set (BUSYCH.BUSYCHn = 1), and it will remain ‘1’ for the subsequent granted beat transfers.
When the channel has performed its granted beat transfer(s), it will either be place back into the queue of channels with pending transfers, set to wait for a new transfer trigger, suspended, or disabled. This behavior depends on the channel and block transfer configuration. If the DMA channel is placed back into the queue of channels with pending transfers, the corresponding BUSYCH.BUSYCHn bit will remain ‘1’. If the DMA channel is set to wait for a new transfer trigger, suspended, or disabled, the corresponding BUSYCH.BUSYCHn bitwill be cleared.
If a DMA channel is suspended while it has a pending transfer, it will be removed from the queue of pending channels, but the corresponding PENDCH.PENDCHn bitwill remain set. When the same DMA channel is resumed, it will be added to the queue of pending channels again.
If a DMA channel is disabled (CHCTRLA.ENABLE = 0) while it has a pending transfer, it will be removed from the queue of pending channels, and the corresponding PENDCH.PENDCHn will be cleared.
Priority Levels
When a channel level is pending or the channel is transferring data, the corresponding Level Executing bit is set in the Active Channel and Levels register (ACTIVE.LVLEXn).
Each DMA channel supports a 4-level priority scheme. The priority level for a channel is configured by writing to the Channel Arbitration Level bit field in the Channel Control B register (CHCTRLB.LVL). As long as all priority levels are enabled, a channel with a higher priority level number will have priority over a channel with a lower priority level number. Each priority level n is enabled by setting the corresponding Priority Level n Enable bit in the Control register (CTRL.LVLENn = 1).
Within each priority level, the DMAC’s arbiter can be configured to prioritize channels either statically or dynamically:
Static arbitration within a priority level is selected by writing a ‘0’ to the Level n Round-Robin Scheduling Enable bit in the Priority Control 0 (PRICTRL0.RRLVLENn) register.
When static arbitration is selected, the arbiter will prioritize lower channel numbers over higher channel numbers as shown Figure 19-5. When using the static arbitration there is a risk that higher channel numbers may never be granted access as the active channel. This riskcan be avoided by using a dynamic arbitration scheme.
Dynamic arbitration within a priority level is selected by writing a ‘1’ to PRICTRL0.RRLVLENn.
The dynamic arbitration scheme in the DMAC is round-robin. With the round-robin scheme, the channel number of the last channel being granted access will have the lowest priority the next time the arbiter must grant access to a channel within the same priority level, as shown Figure 19-6. The channel number of the last channel granted access as the active channel is stored in the Level n Channel Priority Number bit field in the Priority Control 0 (PRICTRL0.LVLPRIn) register for the corresponding priority level.
