19.4.2.4 Transfer Descriptors

Together with the channel configurations, the transfer descriptors determine how a block transfer will be executed. Before a DMA channel is enabled (CHCTRLA.ENABLE is set to ‘1’), and receives a transfer trigger, its first transfer descriptor must be initialized and marked as valid (BTCTRL.VALID). The first transfer descriptor defines the first block transfer of a transaction.

All transfer descriptors must reside in SRAM. The addresses stored in the Descriptor Memory Section Base Address (BASEADDR) and Write-Back Memory Section Base Address (WRBADDR) registers indicate to the DMAC where to find the descriptor memory section and the write-back memory section.

The descriptor memory section is where the DMAC expects to find the first transfer descriptors for all DMA channels. Since BASEADDR only points to the first transfer descriptor of channel 0 (see Figure 19-3), all first transfer descriptors must be stored in a contiguous memory section, ordered according to their channel number. Refer to the Linked Descriptors section for more details.

The write-back memory section is where the DMAC stores the transfer descriptors for ongoing block transfers. WRBADDR points to the ongoing transfer descriptor of channel 0. All ongoing transfer descriptors are stored in a contiguous memory section, ordered according to their channel number. The figure below shows an example of linked descriptors on DMA channel 0. Refer to the Linked Descriptors section for further details.

Note: This device has 2 DMA channels.

The size of the descriptor and write-back memory sections depends on the highest-numbered enabled DMA channel, N, as shown below:

S i z e = 128 bits \cdot (N + 1)

For memory optimization, it is recommended to use the lowest-numbered DMA channels when not all channels are required.

The descriptor and write-back memory sections can either be two separate memory sections, or share the same memory section (BASEADDR = WRBADDR). The benefit of having them in two separate sections is that the same transaction for a channel can be repeated without modifying the first transfer descriptor. The benefit of having descriptor memory and write-back memory in the same section is that it requires less SRAM. Additionally, the latency from fetching the first descriptor of a transaction to the first executed beat transfer is reduced.