19.4.2.6 Data Transaction

Before the DMAC can perform a data transaction, a DMA channel must be configured and enabled, its corresponding transfer descriptor must be initialized, and the arbiter must grant the DMA channel access as the active channel.

Once the arbiter has granted a DMA channel access as the active channel (refer to the DMA Block Diagram section), the transfer descriptor for the DMA channel will be fetched from SRAM using the fetch bus and stored in the internal memory for the active channel. When the transfer starts, the corresponding Channel Busy status flag is set in Channel Status register (CHSTATUS.BUSY).

For a new block transfer, the transfer descriptor will be fetched from the descriptor memory section. Refer to the Descriptor Memory Section Base Address (BASEADDR) register section for more information.

For an ongoing block transfer, the descriptor will be fetched from the write-back memory section. Refer to the Write-Back Memory Section Base Address (WRBADDR) register section for more information.

Using the data transfer bus, the DMAC reads data from the current source address and writes it to the current destination address. Refer to the Addressing section for further details on how the current source and destination addresses are calculated.

The arbitration procedure is performed after each beat transfer. If the current DMA channel is granted access again, the Block Transfer Counter (BTCNT) of the internal transfer descriptor will be decremented by ‘1’, an event output may optionally be generated, and the active channel will perform a new beat transfer. If a different DMA channel is granted access, the block transfer counter value will be written to the write-back section before the transfer descriptor of the newly granted DMA channel is fetched into the internal memory of the active channel.

When a block transfer is complete (BTCNT is ‘0’), the Valid bit in the Block Transfer Control register will be cleared (BTCTRL.VALID = 0) before the entire transfer descriptor is written to the write-back memory. Optional interrupts, Channel Transfer Complete and Channel Suspend, and the optional Block event output, will be generated if configured and enabled. After the last block transfer in a transaction, the Next Descriptor Address (DESCADDR) register will hold the value 0x00000000, and the DMA channel will either be suspended or disabled, depending on the configuration in the Block Action bit field in the Block Transfer Control (BTCNT.BLOCKACT) register. If the transaction has additional block transfers pending, DESCADDR will hold the SRAM address of the next transfer descriptor to be fetched. The DMAC will fetch the next descriptor into the internal memory of the active channel and write its contents to the write-back section for the channel, before the arbiter selects the next active channel.