19.4.2.1 DMA

The DMAC transfers data between memories and peripherals without CPU intervention. The data transferred by the DMAC are called transactions, and these transactions can be divided into smaller data transfers. The following figure illustrates the relationship between the different transfer sizes:

Figure 19-2. DMA Transfer Sizes
  • Beat transfer—The size of a single data transfer bus access; the size is selected by writing to the Beat Size bit field in the Block Transfer Control (BTCTRL.BEATSIZE) register
  • Block transfer—The amount of data one transfer descriptor can transfer, ranging from 1 to 64k beats. A block transfer can be interrupted by a different channel with a higher priority level.
  • Transaction—The DMAC can link several transfer descriptors by having each descriptor point to the next, as shown in the figure above. A DMA transaction is the complete transfer of all blocks within a linked list.

A transfer descriptor specifies the parameters for a block transfer to be executed by the DMAC and must be stored in SRAM. For further details on the transfer descriptor, refer to the Transfer Descriptors section.

The figure above shows several block transfers linked together, which are called linked descriptors. For further information about linked descriptors, refer to the Linked Descriptors section.

A DMA transaction is initiated by an incoming transfer trigger on one of the DMA channels. This trigger can be configured as a software trigger, an event trigger, or a dedicated peripheral trigger. The transfer trigger results in a DMA transfer request from the specific channel to the arbiter. If multiple DMA channels have pending transfer requests, the arbiter selects which channel is granted access to become the active channel. The active channel will carry out the transaction as configured in the transfer descriptor. An ongoing transaction can be interrupted by a higher-prioritiy channel, however, the transaction will resume the block transfer when the lower-prioritiy channel of the DMA channels is granted access as the active channel.

For each beat transfer, an optional event output can be generated. For each block transfer, optional interrupts and an optional event output can be generated. When a transaction is completed, depending on the configuration, the DMA channel will either be suspended or disabled.