19.4.2.8 Addressing

Each block transfer must have both a source address and a destination address defined. The source address is set by writing to the Transfer Source Address (SRCADDR) register, and the destination address is set by writing the Transfer Destination Address (DSTADDR) register.

The addressing of the DMAC can be static or incremental for either source or destination of a block transfer, or for both.

Incrementation for the source address of a block transfer is enabled by writing a ‘1’ to the Source Address Incrementation Enable bit in the Block Transfer Control (BTCTRL.SRCINC) register. The step size for incrementation is configurable and can be changed by writing a ‘1’ to the Step Selection bit in the Block Transfer Control (BTCTRL.STEPSEL) register and selecting the desired step size in the Address Increment Step Size bit field in the Block Transfer Control (BTCTRL.STEPSIZE) register. If BTCTRL.STEPSEL is ‘0’, the step size for source incrementation will be the size of one beat.

When source address incrementation is enabled (BTCTRL.SRCINC = 1), SRCADDR must be set to the ending address and is calculated as follows:

If BTCTRL.STEPSEL = 1:

SRCADDR=SRCADDRSTART⋅BTCNT+BiB⋅2STEPSIZE

If BTCTRL.STEPSEL = 0:

SRCADDR=SRCADDRSTART⋅BTCNT+BiB

Where,

  • SRCADDRSTART is the source address of the first beat transfer in the block transfer
  • BTCNT is the initial number of beats remaining in the block transfer
  • BiB is the configured number of bytes in a beat, as controlled by the BEATSIZE bit field.
  • STEPSIZE is the configured number of beats for each incrementation

Figure 19-8 shows an example where DMA channel 0 is configured to increment the source address by one beat after each beat transfer (BTCTRL.SRCINC = 1), and DMA channel 1 is configured to increment the source address by two beats (BTCTRL.SRCINC = 1, BTCTRL.STEPSEL = 1 and, BTCTRL.STEPSIZE = 0x1). Since the destination address for both channels is a peripheral, destination incrementation is disabled (BTCTRL.DSTINC = 0).

Figure 19-8. Source Address Increment

Incrementation for the destination address of a block transfer is enabled by writing a ‘1’ to the Destination Address Incrementation Enable bit in the Block Transfer Control (BTCTRL.DSTINC) register. The step size for incrementation is configurable by clearing BTCTRL.STEPSEL = 0 and setting BTCTRL.STEPSIZE to the desired step size. If BTCTRL.STEPSEL is set to ‘1’ , the step size for the destination incrementation will be the size of one beat.

When destination address incrementation is enabled (BTCTRL.DSTINC = 1), DSTADDR must be set to the ending address and calculated as follows:

If BTCTRL.STEPSEL = 1:

DSTADDR=DSTADDRSTART⋅BTCNT+BiB

If BTCTRL.STEPSEL = 0:

DSTADDR=DSTADDRSTART⋅BTCNT+BiB⋅2STEPSIZE

Where,

  • DSTADDRSTART is the destination address of the first beat transfer in the block transfer
  • BTCNT is the initial number of beats remaining in the block transfer
  • BiB is the configured number of bytes in a beat, as controlled by the BEATSIZE bit field.
  • STEPSIZE is the configured number of beats for each incrementation

Figure 19-9 shows an example where DMA channel 0 is configured to increment the destination address by one beat (BTCTRL.DSTINC = 1), and DMA channel 1 is configured to increment the destination address by two beats (BTCTRL.DSTINC = 1, BTCTRL.STEPSEL = 0, and BTCTRL.STEPSIZE = 0x1). Since the source address for both channels is a peripheral, source incrementation is disabled (BTCTRL.SRCINC = 0).

Figure 19-9. Destination Address Increment