19.4.2.3 Enabling, Disabling and Resetting

The DMAC is enabled by writing a ‘1’ to the DMA Enable bit in the Control (CTRL.DMAENABLE) register. The DMAC is disabled by writing a ‘0’ to CTRL.DMAENABLE.

A DMA channel is enabled by writing a ‘1’ to the Enable bit in the Channel Control A (CHCTRLA.ENABLE) register, after writing the corresponding channel ID to the Channel ID bit field in the Channel ID (CHID.ID) register. A DMA channel is disabled by writing a ‘0’ to CHCTRLA.ENABLE.

The CRC is enabled by writing a ‘1’ to the CRC Enable bit in the Control (CTRL.CRCENABLE) register. The CRC is disabled by writing a ‘0’ to CTRL.CRCENABLE.

The DMAC is reset by writing a ‘1’ to the Software Reset bit in the Control (CTRL.SWRST) register while both the DMAC and CRC are disabled. All registers in the DMAC, except DBGCTRL, will be reset to their initial state.

A DMA channel is reset by writing a ‘1’ to the Software Reset bit in the Channel Control A (CHCTRLA.SWRST) register, after writing the corresponding channel ID to the Channel ID bit field in the Channel ID (CHID.ID) register. The channel registers will be reset to their initial state. The corresponding DMA channel must be disabled for the reset to take effect.