13.6.1 Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a Read-Modify-Write (RMW) operation.
Changes in this register will also be reflected in the INTENSET register.
| Name: | INTENCLR |
| Offset: | 0x04 |
| Reset: | 0x00000000 |
| Property: | Local Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CLKFAIL | OSC32KRDY | XOSC32KRDY | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
Bit 2 – CLKFAIL XOSC32K Clock Failure Detection Interrupt Enable
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit will clear the
XOSC32K Clock Failure Detection Interrupt Enable bit, which disables the XOSC32K
Clock Failure Detected interrupt.
Bit 1 – OSC32KRDY OSC32K Ready Interrupt Enable
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit will clear the OSC32K Ready Interrupt
Enable bit, which disables the OSC32K Ready interrupt.
Bit 0 – XOSC32KRDY XOSC32K Ready Interrupt Enable
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit will clear the
XOSC32K Ready Interrupt Enable bit, which disables the XOSC32K Ready
interrupt.