13.6.8 Clock Failure Detector Control
| Name: | CFDCTRL |
| Offset: | 0x20 |
| Reset: | 0x00000000 |
| Property: | Local Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CFDPRESC | SWBACK | CFDEN | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
Bit 2 – CFDPRESC Clock Failure Detector Prescaler
This bit selects the prescaler for the clock failure detector.
| Value | Description |
|---|---|
| 0 | The CFD safe clock frequency is equal to the OSC32K frequency |
| 1 | The CFD safe clock frequency is equal to the OSC32K frequency divided by 2 |
Bit 1 – SWBACK Clock Switch Back Enable
This bit controls the XOSC32K output switch back to the external clock or crystal
oscillator in case of clock recovery. This bit cannot be set to
‘1’ until the Clock Failure Detector Enable bit
(CFDCTRL.CFDEN) is set to ‘1’.
This bit is reset once the XOSC32K clock is switched back to the external clock or crystal oscillator.
| Value | Name | Description |
|---|---|---|
| 0 | DISABLE | The clock switch back is disabled |
| 1 | ENABLE | The clock switch back is enabled |
Bit 0 – CFDEN Clock Failure Detector Enable
This bit controls the XOSC32K clock failure detector.
Refer to the Clock Failure Detection Operation section for additional information.
| Value | Name | Description |
|---|---|---|
| 0 | DISABLE | Clock failure detection is disabled |
| 1 | ENABLE | Clock failure detection is enabled |