13.6.3 Interrupt Flag Status and Clear


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
						CLKFAIL	OSC32KRDY	XOSC32KRDY
Access						R/W	R/W	R/W
Reset						0	0	0

Bit 2 – CLKFAIL XOSC32K Clock Failure Detected

This flag is cleared by writing a ‘1’ to it.

This flag is set on a ‘0’-to-’1’ transition of the corresponding flag in the STATUS register and will generate an interrupt request if the INTENSET/CLR.CLKFAIL bit is ‘1’.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the XOSC32K Clock Failure Detected interrupt flag.

Bit 1 – OSC32KRDY OSC32K Ready

This flag is cleared by writing a ‘1’ to it.

This flag is set on a ‘0’-to-’1’ transition of the corresponding flag in the STATUS register and will generate an interrupt request if the INTENSET/CLR.OSC32KRDY bit is ‘1’.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the OSC32K Ready interrupt flag.

Bit 0 – XOSC32KRDY XOSC32K Ready

This flag is cleared by writing a ‘1’ to it.

This flag is set on a ‘0’-to-’1’ transition of the corresponding flag in the STATUS register and will generate an interrupt request if the INTENSET/CLR.XOSC32KRDY bit is ‘1’.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the XOSC32K Ready interrupt flag.

Name:	INTFLAG
Offset:	0x0C
Reset:	0x00000000
Property:	–