10.4.2.3.1 Enabling a Peripheral Clock
Before enabling a peripheral clock, one of the Generators must be enabled (GENCTRL[n].GENEN =
‘1’) and selected as a source for the peripheral channel by setting the
Generator Selection (GEN) bit field of the Peripheral Channel Control (PCHCTRL[n]) register.
Any available Generator can be selected as a clock source for any peripheral channel. Refer
to the following mapping table for mapping of peripherals to index n.
When a Generator has been selected, the peripheral clock is enabled by writing the Channel
Enable bit in the PCHCTRL[n] register (PCHCTRL[n].CHEN) to ‘1’. The CHEN bit
must be synchronized to the generic clock domain. The CHEN bit will continue to read as its
previous state until the synchronization is complete.
The index values of the PCHCTRLm registers are shown in the following table. Use this index to configure the desired generator with the relevant peripheral channel:
| Index [m] | Name | Description |
|---|---|---|
0 | GCLK_EIC | EIC |
1 | GCLK_EVSYS_CHANNEL0 | EVSYS CHANNEL 0 |
2 | GCLK_EVSYS_CHANNEL1 | EVSYS CHANNEL 1 |
3 | GCLK_EVSYS_CHANNEL2 | EVSYS CHANNEL 2 |
4 | GCLK_EVSYS_CHANNEL3 | EVSYS CHANNEL 3 |
5 | GCLK_SERCOM0_SLOW | SERCOM0 SLOW |
6 | GCLK_SERCOM0_CORE | SERCOM0 CORE |
7 | GCLK_SERCOM1_SLOW | SERCOM1 SLOW |
8 | GCLK_SERCOM1_CORE | SERCOM1 CORE |
9 | GCLK_TC0, GCLK_TC1 | TC0, TC1 |
10 | GCLK_TC2 | TC2 |
11 | GCLK_TCC0 | TCC0 |
12 | GCLK_CCL | CCL |
