12.2 Architectural Overview

A general purpose I/O port that shares a pin with a peripheral is generally subservient to the peripheral. Once enabled, the peripheral selects whether the peripheral or the associated port has ownership of the I/O pin.

An MUX and its associated logic controls interaction between peripherals and port logic. When a peripheral is enabled but the peripheral is not actively driving a pin, the port is still allowed to drive the pin. This is useful for “loop through”, in which a port’s digital output drives the input of a peripheral that shares the same pin.

When a peripheral is enabled and actively driving an associated pin, the IO MUX disables the use of the pin as a general purpose output. The I/O pin value may be read by the port, but the LATx[n] output value for the port is ignored.

The output and input circuits of the I/O are independent. The block diagrams of the output and input I/O circuits are shown in Figure 12-1 and Figure 12-2.