12.1 Device-Specific Information

Table 12-1. PORTA Availability
Device	Bit Field	Bit 15/7	Bit 14/6	Bit 13/5	Bit 12/4	Bit 11/3	Bit 10/2	Bit 9/1	Bit 8/0
129-Pin	15:8	✔	✔	✔	✔	✔	✔	✔	✔
129-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
128-Pin	15:8	✔	✔	✔	✔	✔	✔	✔	✔
128-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
100-Pin	15:8	✔	✔	✔	✔	✔	✔	✔	✔
100-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
80-Pin	15:8	✔	✔	✔	✔	✔	✔	✔	✔
80-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
64-Pin	15:8					✔	✔	✔	✔
64-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
48-Pin	15:8							✔	✔
48-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔

Table 12-2. PORTB Availability
Device	Bit Field	Bit 15/7	Bit 14/6	Bit 13/5	Bit 12/4	Bit 11/3	Bit 10/2	Bit 9/1	Bit 8/0
129-Pin	15:8	✔	✔	✔	✔	✔	✔	✔	✔
129-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
128-Pin	15:8	✔	✔	✔	✔	✔	✔	✔	✔
128-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
100-Pin	15:8	✔	✔	✔	✔	✔	✔	✔	✔
100-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
80-Pin	15:8	✔	✔	✔	✔	✔	✔	✔	✔
80-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
64-Pin	15:8					✔	✔	✔	✔
64-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
48-Pin	15:8
48-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔

Table 12-3. PORTC Availability
Device	Bit Field	Bit 15/7	Bit 14/6	Bit 13/5	Bit 12/4	Bit 11/3	Bit 10/2	Bit 9/1	Bit 8/0
129-Pin	15:8	✔	✔	✔	✔	✔	✔	✔	✔
129-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
128-Pin	15:8	✔	✔	✔	✔	✔	✔	✔	✔
128-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
100-Pin	15:8	✔	✔	✔	✔	✔	✔	✔	✔
100-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
80-Pin	15:8			✔	✔	✔	✔	✔	✔
80-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
64-Pin	15:8					✔	✔	✔	✔
64-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
48-Pin	15:8
48-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔

Table 12-4. PORTD Availability
Device	Bit Field	Bit 15/7	Bit 14/6	Bit 13/5	Bit 12/4	Bit 11/3	Bit 10/2	Bit 9/1	Bit 8/0
129-Pin	15:8	✔	✔	✔	✔	✔	✔	✔	✔
129-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
128-Pin	15:8	✔	✔	✔	✔	✔	✔	✔	✔
128-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
100-Pin	15:8	✔	✔	✔	✔	✔	✔	✔	✔
100-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
80-Pin	15:8				✔	✔	✔	✔	✔
80-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
64-Pin	15:8								✔
64-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
48-Pin	15:8
48-Pin	7:0		✔			✔	✔	✔	✔

Table 12-5. PORTE Availability
Device	Bit Field	Bit 15/7	Bit 14/6	Bit 13/5	Bit 12/4	Bit 11/3	Bit 10/2	Bit 9/1	Bit 8/0
129-Pin	15:8						✔	✔	✔
129-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
128-Pin	15:8						✔	✔	✔
128-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
100-Pin	15:8
100-Pin	7:0				✔	✔	✔	✔	✔
80-Pin	15:8
80-Pin	7:0
64-Pin	15:8
64-Pin	7:0
48-Pin	15:8
48-Pin	7:0

Table 12-6. PORTF Availability
Device	Bit Field	Bit 15/7	Bit 14/6	Bit 13/5	Bit 11/3	Bit 10/2	Bit 9/1	Bit 8/0
129-Pin	15:8				✔	✔	✔	✔
129-Pin	7:0	✔	✔	✔	✔	✔	✔	✔
128-Pin	15:8				✔	✔	✔	✔
128-Pin	7:0	✔	✔	✔	✔	✔	✔	✔
100-Pin	15:8
100-Pin	7:0				✔	✔	✔	✔
80-Pin	15:8
80-Pin	7:0
64-Pin	15:8
64-Pin	7:0
48-Pin	15:8
48-Pin	7:0

Table 12-7. PORTG Availability
Device	Bit Field	Bit 15/7	Bit 14/6	Bit 13/5	Bit 12/4	Bit 10/2	Bit 9/1	Bit 8/0
129-Pin	15:8						✔	✔
129-Pin	7:0	✔	✔	✔	✔	✔	✔	✔
128-Pin	15:8						✔	✔
128-Pin	7:0	✔	✔	✔	✔	✔	✔	✔
100-Pin	15:8
100-Pin	7:0					✔	✔	✔
80-Pin	15:8
80-Pin	7:0
64-Pin	15:8
64-Pin	7:0
48-Pin	15:8
48-Pin	7:0

Table 12-8. PORTH Availability
Device	Bit Field	Bit 10/2	Bit 9/1	Bit 8/0
129-Pin	15:8
129-Pin	7:0	✔	✔	✔
128-Pin	15:8
128-Pin	7:0	✔	✔	✔
100-Pin	15:8
100-Pin	7:0
80-Pin	15:8
80-Pin	7:0
64-Pin	15:8
64-Pin	7:0
48-Pin	15:8
48-Pin	7:0

Table 12-9. ANSELA Availability
Name	Bit Field	Bit 15/7	Bit 14/6	Bit 13/5	Bit 12/4	Bit 11/3	Bit 10/2	Bit 9/1	Bit 8/0
129-Pin	15:8	✔	✔	✔	✔	✔	✔	✔	✔
129-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
128-Pin	15:8	✔	✔	✔	✔	✔	✔	✔	✔
128-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
100-Pin	15:8	✔	✔	✔	✔	✔	✔	✔	✔
100-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
80-Pin	15:8	✔	✔	✔	✔	✔	✔	✔	✔
80-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
64-Pin	15:8					✔	✔	✔	✔
64-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
48-Pin	15:8							✔	✔
48-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔

Table 12-10. ANSELB Availability
Name	Bit Field	Bit 15/7	Bit 14/6	Bit 13/5	Bit 12/4	Bit 11/3	Bit 10/2	Bit 9/1	Bit 8/0
129-Pin	15:8	✔	✔	✔	✔	✔	✔	✔	✔
129-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
128-Pin	15:8	✔	✔	✔	✔	✔	✔	✔	✔
128-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
100-Pin	15:8	✔	✔	✔	✔	✔	✔	✔	✔
100-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
80-Pin	15:8	✔	✔	✔	✔	✔	✔	✔	✔
80-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
64-Pin	15:8					✔	✔	✔	✔
64-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔
48-Pin	15:8
48-Pin	7:0	✔	✔	✔	✔	✔	✔	✔	✔

Table 12-11. ANSELC Availability
Name	Bit Field	Bit 15/7	Bit 14/6	Bit 13/5	Bit 12/4	Bit 11/3	Bit 10/2	Bit 9/1	Bit 8/0
129-Pin	15:8
129-Pin	7:0
128-Pin	15:8
128-Pin	7:0
100-Pin	15:8
100-Pin	7:0
80-Pin	15:8
80-Pin	7:0
64-Pin	15:8
64-Pin	7:0
48-Pin	15:8
48-Pin	7:0

Table 12-12. ANSELD Availability
Name	Bit Field	Bit 15/7	Bit 14/6	Bit 13/5	Bit 12/4	Bit 11/3	Bit 10/2	Bit 9/1	Bit 8/0
129-Pin	15:8
129-Pin	7:0
128-Pin	15:8
128-Pin	7:0
100-Pin	15:8
100-Pin	7:0
80-Pin	15:8
80-Pin	7:0
64-Pin	15:8
64-Pin	7:0
48-Pin	15:8
48-Pin	7:0

Table 12-13. ANSELE Availability
Name	Bit Field	Bit 9/1	Bit 8/0
129-Pin	15:8
129-Pin	7:0	✔	✔
128-Pin	15:8
128-Pin	7:0	✔	✔
100-Pin	15:8
100-Pin	7:0	✔	✔
80-Pin	15:8
80-Pin	7:0
64-Pin	15:8
64-Pin	7:0
48-Pin	15:8
48-Pin	7:0

Table 12-14. ANSELF Availability
Name	Bit Field	Bit 8/0
129-Pin	15:8
129-Pin	7:0	✔
128-Pin	15:8
128-Pin	7:0	✔
100-Pin	15:8
100-Pin	7:0	✔
80-Pin	15:8
80-Pin	7:0
64-Pin	15:8
64-Pin	7:0
48-Pin	15:8
48-Pin	7:0

Table 12-15. ANSELG Availability
Name	Bit Field	Bit 15/7	Bit 14/6	Bit 13/5	Bit 12/4	Bit 11/3	Bit 10/2	Bit 9/1	Bit 8/0
129-Pin	15:8
129-Pin	7:0
128-Pin	15:8
128-Pin	7:0
100-Pin	15:8
100-Pin	7:0
80-Pin	15:8
80-Pin	7:0
64-Pin	15:8
64-Pin	7:0
48-Pin	15:8
48-Pin	7:0

Table 12-16. ANSELH Availability
Name	Bit Field	Bit 15/7	Bit 14/6	Bit 13/5	Bit 12/4	Bit 11/3	Bit 10/2	Bit 9/1	Bit 8/0
129-Pin	15:8
129-Pin	7:0
128-Pin	15:8
128-Pin	7:0
100-Pin	15:8
100-Pin	7:0
80-Pin	15:8
80-Pin	7:0
64-Pin	15:8
64-Pin	7:0
48-Pin	15:8
48-Pin	7:0

Table 12-17. PPS Availability by Package
129-Pin	128-Pin	100-Pin	80-Pin	64-Pin	48-Pin
RP1-RP75	RP1-RP75	RP1-RP69	RP1-RP46	RP1-RP12	RP1-RP10
RP81-RP84	RP81-RP84	RP81-RP84	RP49-RP61	RP17-RP28	RP17-RP24
RP86-RP92	RP86-RP92	RP97-RP99		RP33-RP44	RP33-RP40
RP97-RP99	RP97-RP99			RP49-RP57	RP49-RP52
RP101-RP106	RP101-RP106				RP55
RP113-RP115	RP113-RP115

Table 12-18. Selectable Input Sources (Maps Input to Function)
Input Name⁽¹⁾	Function Name	Register	Register Bitfield
External Interrupt 1	INT1	RPINR0	INT1R[7:0]
External Interrupt 2	INT2	RPINR0	INT2R[7:0]
External Interrupt 3	INT3	RPINR0	INT3R[7:0]
External Interrupt 4	INT4	RPINR1	INT4R[7:0]
Timer1 External Clock	T1CK	RPINR1	T1CKR[7:0]
Timer2 External Clock	T2CK	RPINR1	T2CKR[7:0]
Timer3 External Clock	T3CK	RPINR1	T3CKR[7:0]
SCCP Input Clock 1	TCKI1	RPINR2	TCKI1R[7:0]
SCCP Input Capture 1	ICM1	RPINR2	ICM1R[7:0]
SCCP Input Clock 2	TCKI2	RPINR2	TCKI2R[7:0]
SCCP Input Capture 2	ICM2	RPINR2	ICM2R[7:0]
SCCP Input Clock 3	TCKI3	RPINR3	TCKI3R[7:0]
SCCP Input Capture 3	ICM3	RPINR3	ICM3R[7:0]
SCCP Input Clock 4	TCKI4	RPINR3	TCKI4R[7:0]
SCCP Input Capture 4	ICM4	RPINR3	ICM4R[7:0]
SCCP Input Clock 5	TCKI5	RPINR4	TCKI5R[7:0]
SCCP Input Capture 5	ICM5	RPINR4	ICM5R[7:0]
SCCP Input Clock 6	TCKI6	RPINR4	TCKI6R[7:0]
SCCP Input Capture 6	ICM6	RPINR4	ICM6R[7:0]
SCCP Input Clock 7	TCKI7	RPINR5	TCKI7R[7:0]
SCCP Input Capture 7	ICM7	RPINR5	ICM7R[7:0]
SCCP Input Clock 8	TCKI8	RPINR5	TCKI8R[7:0]
SCCP Input Capture 8	ICM8	RPINR5	ICM8R[7:0]
MCCP Input Clock 9	TCKI9	RPINR6	TCKI9R[7:0]
MCCP Input Capture 9	ICM9	RPINR6	ICM9R[7:0]
Reserved
SCCP Fault A	OCFA	RPINR7	OCFAR[7:0]
SCCP Fault B	OCFB	RPINR7	OCFBR[7:0]
SCCP Fault C	OCFC	RPINR7	OCFCR[7:0]
SCCP Fault D	OCFD	RPINR7	OCFDR[7:0]
PWM Input 8	PCI8	RPINR8	PCI8R[7:0]
PWM Input 9	PCI9	RPINR8	PCI9R[7:0]
PWM Input 10	PCI10	RPINR8	PCI10R[7:0]
PWM Input 11	PCI11	RPINR8	PCI11R[7:0]
QEI1 Input A	QEIA1	RPINR9	QEIA1R[7:0]
QEI1 Input B	QEIB1	RPINR9	QEIB1R[7:0]
QEI1 Index Input	QEINDX1	RPINR9	QEINDX1R[7:0]
QEI1 Home Input	QEIHOME1	RPINR9	QEIHOM1R[7:0]
QEI2 Input A	QEIA2	RPINR10	QEIA2R[7:0]
QEI2 Input B	QEIB2	RPINR10	QEIB2R[7:0]
QEI2 Index Input	QEINDX2	RPINR10	QEINDX2R[7:0]
QEI2 Home Input	QEIHOME2	RPINR10	QEIHOM2R[7:0]
QEI3 Input A	QEIA3	RPINR11	QEIA3R[7:0]
QEI3 Input B	QEIB3	RPINR11	QEIB3R[7:0]
QEI3 Index Input	QEINDX3	RPINR11	QEINDX3R[7:0]
QEI3 Home Input	QEIHOME3	RPINR11	QEIHOM3R[7:0]
QEI4 Input A	QEIA4	RPINR12	QEIA4R[7:0]
QEI4 Input B	QEIB4	RPINR12	QEIB4R[7:0]
QEI4 Index Input	QEINDX4	RPINR12	QEINDX4R[7:0]
QEI4 Home Input	QEIHOME4	RPINR12	QEIHOM4R[7:0]
UART1 Receive	U1RX	RPINR13	U1RXR[7:0]
UART1 Data-Set-Ready	U1DSR	RPINR13	U1DSRR[7:0]
UART2 Receive	U2RX	RPINR13	U2RXR[7:0]
UART2 Data-Set-Ready	U2DSR	RPINR13	U2DSRR[7:0]
UART3 Receive	U3RX	RPINR14	U3RXR[7:0]
UART3 Data-Set-Ready	U3DSR	RPINR14	U3DSRR[7:0]
SPI1 Data Input	SDI1	RPINR14	SDI1R[7:0]
SPI1 Clock Input	SCK1IN	RPINR14	SCK1R[7:0]
SPI1 Client Select	SS1IN	RPINR15	SS1R[7:0]
SPI2 Data Input	SDI2	RPINR15	SDI2R[7:0]
SPI2 Clock Input	SCK2IN	RPINR15	SCK2R[7:0]
SPI2 Client Select	SS2IN	RPINR15	SS2R[7:0]
SPI3 Data Input	SDI3	RPINR16	SDI3R[7:0]
SPI3 Clock Input	SCK3IN	RPINR16	SCK3R[7:0]
SPI3 Client Select	SS3IN	RPINR16	SS3R[7:0]
SPI4 Data Input	SDI4	RPINR16	SDI4R[7:0]
SPI4 Clock Input	SCK4IN	RPINR17	SCK4R[7:0]
SPI4 Client Select	SS4IN	RPINR17	SS4R[7:0]
CAN 1 Receive	CAN1RX	RPINR17	CAN1RXR[7:0]
CAN 2 Receive	CAN2RX	RPINR17	CAN2RXR[7:0]
SENT 1 Input	SENT1	RPINR18	SENT1R[7:0]
SENT 2 Input	SENT2	RPINR18	SENT2R[7:0]
Reference Clock 1 Input	REFI1	RPINR18	REFI1R[7:0]
Reference Clock 2 Input	REFI2	RPINR18	REFI2R[7:0]
PWM Input 12	PCI12	RPINR19	PCI12R[7:0]
PWM Input 13	PCI13	RPINR19	PCI13R[7:0]
PWM Input 14	PCI14	RPINR19	PCI14R[7:0]
PWM Input 15	PCI15	RPINR19	PCI15R[7:0]
PWM Input 16	PCI16	RPINR20	PCI16R[7:0]
PWM Input 17	PCI17	RPINR20	PCI17R[7:0]
PWM Input 18	PCI18	RPINR20	PCI18R[7:0]
CLC Input A	CLCINA	RPINR20	CLCAR[7:0]
CLC Input B	CLCINB	RPINR21	CLCBR[7:0]
CLC Input C	CLCINC	RPINR21	CLCCR[7:0]
CLC Input D	CLCIND	RPINR21	CLCDR[7:0]
CLC Input E	CLCINE	RPINR21	CLCER[7:0]
CLC Input F	CLCINF	RPINR22	CLCFR[7:0]
CLC Input G	CLCING	RPINR22	CLCGR[7:0]
CLC Input H	CLCINH	RPINR22	CLCHR[7:0]
CLC Input I	CLCINI	RPINR22	CLCIR[7:0]
CLC Input J	CLCINJ	RPINR23	CLCJR[7:0]
ADC Trigger 31 Input	ADTRG31	RPINR23	ADTRG31R[7:0]
UART1 Clear to Send	U1CTS	RPINR23	U1CTSR[7:0]
UART2 Clear to Send	U2CTS	RPINR23	U2CTSR[7:0]
UART3 Clear to Send	U3CTS	RPINR24	U3CTSR[7:0]
BiSS Return Input	BISS1SL	RPINR24	BISS1SLR[7:0]
BiSS Get Sense Input	BISS1GS	RPINR24	BISS1GSR[7:0]
IOMONITOR1 Feedback 12	IOMON1F12	RPINR24	IOIM0R[7:0]
IOMONITOR1 Feedback 13	IOMON1F13	RPINR25	IOIM1R[7:0]
IOMONITOR1 Feedback 14	IOMON1F14	RPINR25	IOIM2R[7:0]
IOMONITOR1 Feedback 15	IOMON1F15	RPINR25	IOIM3R[7:0]
IOMONITOR2 Feedback 12	IOMON2F12	RPINR25	IOIM4R[7:0]
IOMONITOR2 Feedback 13	IOMON2F13	RPINR26	IOIM5R[7:0]
IOMONITOR2 Feedback 14	IOMON2F14	RPINR26	IOIM6R[7:0]
IOMONITOR2 Feedback 15	IOMON2F15	RPINR26	IOIM7R[7:0]
PWM Input 19	PCI19	RPINR26	PCI19R[7:0]
PWM Input 20	PCI20	RPINR27	PCI20R[7:0]
PWM Input 21	PCI21	RPINR27	PCI21R[7:0]
PWM Input 22	PCI22	RPINR27	PCI22R[7:0]
Note: Unless otherwise noted, all inputs use the Schmitt Trigger input buffers.

Table 12-19. Pin Correlation to Input Remap #⁽¹⁾
Index	Source Signal	Remap Input #
181	RPV15	PI181
180	RPV14	PI180
179	RPV13	PI179
178	RPV12	PI178
177	RPV11	PI177
176	RPV10	PI176
175	RPV9	PI175
174	RPV8	PI174
173	RPV7	PI173
172	RPV6	PI172
171	RPV5	PI171
170	RPV4	PI170
169	RPV3	PI169
168	RPV2	PI168
167	RPV1	PI167
166	RPV0	PI166
165	Touch TX8	PI165
164	Touch TX9	PI164
163	Touch TX10	PI163
162	Touch TX11	PI162
161	Touch TX12	PI161
160	Touch TX13	PI160
159	Touch TX14	PI159
158	Touch TX15	PI158
157	pwm_req_off[8] (from DAC8)	PI157
156	pwm_req_on[8] (from DAC8)	PI156
155	pwm_req_off[7] (from DAC7)	PI155
154	pwm_req_on[7] (from DAC7)	PI154
153	pwm_req_off[6] (from DAC6)	PI153
152	pwm_req_on[6] (from DAC6)	PI152
151	pwm_req_off[5] (from DAC5)	PI151
150	pwm_req_on[5] (from DAC5)	PI150
149	pwm_req_off[4] (from DAC4)	PI149
148	pwm_req_on[4] (from DAC4)	PI148
147	pwm_req_off[3] (from DAC3)	PI147
146	pwm_req_on[3] (from DAC3)	PI146
145	pwm_req_off[2] (from DAC2)	PI145
144	pwm_req_on[2] (from DAC2)	PI144
143	pwm_req_off[1] (from DAC1)	PI143
142	pwm_req_on[1] (from DAC1)	PI142
141	apwm_event_out[1]	PI141
140	pwm_event_out[2]	PI140
139	pwm_event_out[1]	PI139
138	PTG TRIG[27]	PI138
137	PTG TRIG[26]	PI137
136	CMP8	PI136
135	CMP7	PI135
134	CMP6	PI134
133	CMP5	PI133
132	CMP4	PI132
131	CMP3	PI131
130	CMP2	PI130
129	CMP1	PI129
115	RH2	PI115
114	RH1	PI114
113	RH0	PI113
106	RG9	PI106
105	RG8	PI105
104	RG7	PI104
103	RG6	PI103
102	RG5	PI102
101	RG4	PI101
99	RG2	PI99
98	RG1	PI98
97	RG0	PI97
92	RF11	PI92
91	RF10	PI91
90	RF9	PI90
89	RF8	PI89
88	RF7	PI88
87	RF6	RPI87
86	RF5	RPI86
84	RF3	RPI84
83	RF2	RPI83
82	RF1	RPI82
81	RF0	RPI81
75	RE10	RPI75
74	RE9	RPI74
73	RE8	RPI73
72	RE7	RPI72
71	RE6	RPI71
70	RE5	RPI70
69	RE4	RPI69
68	RE3	RPI68
67	RE2	RPI67
66	RE1	RPI66
65	RE0	RPI65
64	RD15	RPI64
63	RD14	RPI63
62	RD13	RPI62
61	RD12	RPI61
60	RD11	RPI60
59	RD10	RPI59
58	RD9	RPI58
57	RD8	RPI57
56	RD7	RPI56
55	RD6	RPI55
54	RD5	RPI54
53	RD4	RPI53
52	RD3	RPI52
51	RD2	RPI51
50	RD1	RPI50
49	RD0	RPI49
48	RC15	RPI48
47	RC14	RPI47
46	RC13	RPI46
45	RC12	RPI45
44	RC11	RPI44
43	RC10	RPI43
42	RC9	RPI42
41	RC8	RPI41
40	RC7	RPI40
39	RC6	RPI39
38	RC5	RPI38
37	RC4	RPI37
36	RC3	RPI36
35	RC2	RPI35
34	RC1	RPI34
33	RC0	RPI33
32	RB15	RPI32
31	RB14	RPI31
30	RB13	RPI30
29	RB12	RPI29
28	RB11	RPI28
27	RB10	RPI27
26	RB9	RPI26
25	RB8	RPI25
24	RB7	RPI24
23	RB6	RPI23
22	RB5	RPI22
21	RB4	RPI21
20	RB3	RPI20
19	RB2	RPI19
18	RB1	RPI18
17	RB0	RPI17
16	RA15	RPI16
15	RA14	RPI15
14	RA13	RPI14
13	RA12	RPI13
12	RA11	RPI12
11	RA10	RPI11
10	RA9	RPI10
9	RA8	RPI9
8	RA7	RPI8
7	RA6	RPI7
6	RA5	RPI6
5	RA4	RPI5
4	RA3	RPI4
3	RA2	RPI3
2	RA1	RPI2
1	RA0	RPI1
Note: This list of output signals can be mapped to any of the peripheral inputs listed in Table 12-18.

Table 12-20. Virtual Outputs to Remappable Ouput Registers⁽¹⁾
Virtual Outputs	Remappable Output Register	Register Bitfield
RPV0	RPOR32	RP129R[6:0]
RPV1	RPOR32	RP130R[6:0]
RPV2	RPOR32	RP131R[6:0]
RPV3	RPOR32	RP132R[6:0]
RPV4	RPOR33	RP133R[6:0]
RPV5	RPOR33	RP134R[6:0]
RPV6	RPOR33	RP135R[6:0]
RPV7	RPOR33	RP136R[6:0]
RPV8	RPOR34	RP137R[6:0]
RPV9	RPOR34	RP138R[6:0]
RPV10	RPOR34	RP139R[6:0]
RPV11	RPOR34	RP140R[6:0]
RPV12	RPOR35	RP141R[6:0]
RPV13	RPOR35	RP142R[6:0]
RPV14	RPOR35	RP143R[6:0]
RPV15	RPOR35	RP144R[6:0]
Note: This list of virtual output signals can be mapped to any of the peripheral inputs listed in Table 12-18.

Table 12-21. Output Selection for Remappable Pins (RPn)
Function	RPnR[5:0]	Output Name
Default PORT	0	RPn tied to Default Pin
PWM1H	1	RPn tied to PWM1H Output
PWM1L	2	RPn tied to PWM1L Output
PWM2H	3	RPn tied to PWM2H Output
PWM2L	4	RPn tied to PWM2L Output
PWM3H	5	RPn tied to PWM3H Output
PWM3L	6	RPn tied to PWM3L Output
PWM4H	7	RPn tied to PWM4H Output
PWM4L	8	RPn tied to PWM4L Output
PWM5H	9	RPn tied to PWM5H Output
PWM5L	10	RPn tied to PWM5L Output
PWM6H	11	RPn tied to PWM6H Output
PWM6L	12	RPn tied to PWM6L Output
PWM7H	13	RPn tied to PWM7H Output
PWM7L	14	RPn tied to PWM7L Output
PWM8H	15	RPn tied to PWM8H Output
PWM8L	16	RPn tied to PWM8L Output
CAN1TX	17	RPn tied to CAN1 Output
CAN2TX	18	RPn tied to CAN2 Output
U1TX	19	RPn tied to UART1 Transmit
U1RTS	20	RPn tied to UART1 Request-to-Send
U2TX	21	RPn tied to UART2 Transmit
U2RTS	22	RPn tied to UART2 Request-to-Send
U3TX	23	RPn tied to UART3 Transmit
U3RTS	24	RPn tied to UART3 Request-to-Send
SDO1	25	RPn tied to SPI1 Data Output
SCK1	26	RPn tied to SPI1 Clock Output
SS1	27	RPn tied to SPI1 Client Select
SDO2	28	RPn tied to SPI2 Data Output
SCK2	29	RPn tied to SPI2 Clock Output
SS2	30	RPn tied to SPI21 Client Select
SDO3	31	RPn tied to SPI3 Data Output
SCK3	32	RPn tied to SPI3 Clock Output
SS3	33	RPn tied to SPI3 Client Select
SDO4	34	RPn tied to SPI4 Data Output
SCK4	35	RPn tied to SPI4 Clock Output
SS4	36	RPn tied to SPI4 Client Select
REFO1	37	RPn tied to Reference Clock 1 Output
REFO2	38	RPn tied to Reference Clock 2 Output
OCM1	39	RPn tied to SCCP1 Output
OCM2	40	RPn tied to SCCP2 Output
OCM3	41	RPn tied to SCCP3 Output
OCM4	42	RPn tied to SCCP4 Output
OCM5	43	RPn tied to SCCP5 Output
OCM6	44	RPn tied to SCCP6 Output
OCM7	45	RPn tied to SCCP7 Output
OCM8	46	RPn tied to SCCP8 Output
MCCP9A	47	RPn tied to MCCP9 Output A
MCCP9B	48	RPn tied to MCCP9 Output B
MCCP9C	49	RPn tied to MCCP9 Output C
MCCP9D	50	RPn tied to MCCP9 Output D
MCCP9E	51	RPn tied to MCCP9 Output E
MCCP9F	52	RPn tied to MCCP9 Output F
CMP1	53	RPn tied to Comparator 1 Output
CMP2	54	RPn tied to Comparator 2 Output
CMP3	55	RPn tied to Comparator 3 Output
CMP4	56	RPn tied to Comparator 4 Output
CMP5	57	RPn tied to Comparator 5 Output
CMP6	58	RPn tied to Comparator 6 Output
CMP7	59	RPn tied to Comparator 7 Output
CMP8	60	RPn tied to Comparator 8 Output
PEVTA	61	RPn tied to PWM Event A Output
PEVTB	62	RPn tied to PWM Event B Output
PEVTC	63	RPn tied to PWM Event C Output
PEVTD	64	RPn tied to PWM Event D Output
QEICMP1	65	RPn tied to QEI1 Comparator Output
QEICMP2	66	RPn tied to QEI2 Comparator Output
QEICMP3	67	RPn tied to QEI3 Comparator Output
QEICMP4	68	RPn tied to QEI4 Comparator Output
CLC1OUT	69	RPn tied to CLC1 Output
CLC2OUT	70	RPn tied to CLC2 Output
CLC3OUT	71	RPn tied to CLC3 Output
CLC4OUT	72	RPn tied to CLC4 Output
CLC5OUT	73	RPn tied to CLC5 Output
CLC6OUT	74	RPn tied to CLC6 Output
CLC7OUT	75	RPn tied to CLC7 Output
CLC8OUT	76	RPn tied to CLC18 Output
CLC9OUT	77	RPn tied to CLC9 Output
CLC10OUT	78	RPn tied to CLC10 Output
PTGTRG24	79	RPn tied to PTG Trigger 24 Output
PTGTRG25	80	RPn tied to PTG Trigger 25 Output
SENT1OUT	81	RPn tied to SENT1 Output
SENT2OUT	82	RPn tied to SENT2 Output
BISSMO1	83	RPn tied to BiSS Line Digital Output 1 Enable
BISSMA1	84	RPn tied to BiSS Line Digital Clock 1
U1DTR	85	RPn tied to UART1 Data Terminal Ready Output
U2DTR	86	RPn tied to UART2 Data Terminal Ready Output
U3DTR	87	RPn tied to UART3 Data Terminal Ready Output
APWM1H	88	RPn tied to Auxiliary PWM1H Output
APWM1L	89	RPn tied to Auxiliary PWM1L Output
APWM2H	90	RPn tied to Auxiliary PWM2H Output
APWM2L	91	RPn tied to Auxiliary PWM2L Output
APWM3H	92	RPn tied to Auxiliary PWM3H Output
APWM3L	93	RPn tied to Auxiliary PWM3L Output
APWM4H	94	RPn tied to Auxiliary PWM4H Output
APWM4L	95	RPn tied to Auxiliary PWM4L Output
APEVTA	96	RPn tied to APWM Event A
APEVTB	97	RPn tied to APWM Event B

Table 12-22. IOIM 1-8 Group A Reference Pins
REFSEL	Pin Function Name	Pad
`1111`	IOMAD15	RPV3
`1110`	IOMAD14	RPV2
`1101`	IOMAD13	RPV1
`1100`	IOMAD12	RPV0
`1011`	IOMAD11	RD14
`1010`	IOMAD10	RD15
`1001`	IOMAD9	RD11
`1000`	IOMAD8	RC8
`0111`	IOMAD7	RC2
`0110`	IOMAD6	RC5
`0101`	IOMAD5	RC3
`0100`	IOMAD4	RC4
`0011`	IOMAD3	RD0
`0010`	IOMAD2	RD1
`0001`	IOMAD1	RD2
`0000`	IOMAD0	RD3

Table 12-23. IOIM 1-8 Group A Feedback Pins
FBKSEL	Pin Function Name	Pad
`1111`	IOMAF15	IOM3R[7:0]
`1110`	IOMAF14	IOM2R[7:0]
`1101`	IOMAF13	IOM1R[7:0]
`1100`	IOMAF12	IOM0R[7:0]
`1011`	IOMAF11	RB10
`1010`	IOMAF10	RB11
`1001`	IOMAF9	RD10
`1000`	IOMAF8	RD11
`0111`	IOMAF7	RC7
`0110`	IOMAF6	RC1
`0101`	IOMAF5	RC0
`0100`	IOMAF4	RD7
`0011`	IOMAF3	RD8
`0010`	IOMAF2	RA0
`0001`	IOMAF1	RA7
`0000`	IOMAF0	RB7

Table 12-24. IOIM 9-16 Group B Reference Pins
REFSEL	Pin Function Name	Pad
`1111`	IOMBD15	RPV7
`1110`	IOMBD14	RPV6
`1101`	IOMBD13	RPV5
`1100`	IOMBD12	RPV4
`1011`	IOMBD11	RG1
`1010`	IOMBD10	RG2
`1001`	IOMBD9	RC14
`1000`	IOMBD8	RC15
`0111`	IOMBD7	RC12
`0110`	IOMBD6	RC13
`0101`	IOMBD5	RC10
`0100`	IOMBD4	RC11
`0011`	IOMBD3	RD9
`0010`	IOMBD2	RD10
`0001`	IOMBD1	RD5
`0000`	IOMBD0	RD6

Table 12-25. IOIM 9-16 Group B Feedback Pins
FBKSEL	Pin Function Name	Pad
`1111`	IOMBF15	IOM7R[7:0]
`1110`	IOMBF14	IOM6R[7:0]
`1101`	IOMBF13	IOM5R[7:0]
`1100`	IOMBF12	IOM4R[7:0]
`1011`	IOMBF11	RB10
`1010`	IOMBF10	RB11
`1001`	IOMBF9	RD10
`1000`	IOMBF8	RD11
`0111`	IOMBF7	RD9
`0110`	IOMBF6	RD4
`0101`	IOMBF5	RD15
`0100`	IOMBF4	RD13
`0011`	IOMBF3	RC8
`0010`	IOMBF2	RC9
`0001`	IOMBF1	RC10
`0000`	IOMBF0	RC11