20.4.2 Pulse Density Modulation (PDM) DAC

Each instance of the High-Speed Analog Comparator with the Slope Compensation DAC has a dedicated DAC that is used to program the comparator threshold voltage via the DACxDAT register. The DAC comprises a digital Pulse Density Modulation (PDM) module, followed by a multistage RC filter. The PDM module generates a high-frequency output signal whose density is proportional to the DACxDAT register value.

The DACHIGH[15:0] data limits in the DACxDAT register are bound between 0x0CD and 0xF32 leading to a DAC output of 5% to 95% of V_DD. For any intermediate value between 0xCD and 0xF32, the output voltage of the DAC will be proportional. The equation to calculate the DAC output voltage based on V_DD voltage source is provided in Equation 19-1. The DAC voltage can be varied in steps of V_DD/(2N – 1), where N is the number of DAC bits (N = 12). The DAC modules as a whole are controlled by the ON bit (DACCTRL1[15]). The ON bit enables or disables all comparator/DAC modules instantiated on a given device or device core. The DACEN bit (DACxCON[15]) provides individual control of the DAC module. The individual DAC registers have an output enable bit, DACOEN (DACxCON[8]), which enables the DAC output voltage to be routed to an external output pin, DACOUTx. The DACOUTx pin can only be associated with a single DAC. If more than one DACOEN bit is set, the DACOUTx pin will be a combination of the signals. For devices with more than one DAC output buffer, the odd numbered DAC outputs connect to DACOUT1 with the even channels connecting to DACOUT2. A configuration example to set the DAC output voltage is shown in Configuration of DAC Register.

/* DAC Register Settings */
DAC1DATbits.DAC1DATbits.DACHIGH = 0x4D9;	   /* DAC Output set to 1V (VDD = 3.3V)*/
DAC1CONbits.DACOEN = 1;				/* Enable DAC 1 output on pin DACOUT1 */
DAC1CONbits.DACEN = 1;				 /* Enable DAC 1 */
DACCTRL1bits.ON = 1				    /* Turn ON all DACs */