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dsPIC33AK512MPS512 Family Data Sheet
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11
Interrupt Controller
11.10
Interrupt Operations
11.10.5
Interrupt Setup Procedures
Operating Conditions
High-Performance dsPIC33A DSP/RISC CPU
Memory Features
Security Features
High-Speed PWM
High-Speed Analog-to-Digital Converters
Peripheral Features
Controller Features
Analog Features
Safety Features
Functional Safety Support
Qualification
Programming and Debug Interfaces
dsPIC33AK512MPS512
Family Features
Pin Diagrams
1
Pinout I/O Descriptions
2
Device Overview
3
Guidelines for Getting Started with Digital Signal Controllers
4
CPU
5
Memory Organization
6
Data Memory
7
Flash Program Memory
8
Configuration Bits
9
Security Module
10
Resets
11
Interrupt Controller
11.1
Device-Specific Information
11.2
Architectural Overview
11.3
Interrupt Vector Table
11.4
Register Summary
11.5
Operation
11.6
Interrupt Control and Status Registers
11.7
Priority
11.8
Interrupt Sequence
11.9
Non-Maskable Traps
11.10
Interrupt Operations
11.10.1
Disabling Interrupts
11.10.2
External Interrupt Requests
11.10.3
Wake-Up From Sleep, Idle
11.10.4
Interrupt Processing Timing
11.10.5
Interrupt Setup Procedures
11.10.5.1
Initialization
11.10.5.2
Interrupt Service Routine
11.10.5.3
Trap Service Routine
11.10.5.4
Code Examples
12
I/O Ports with Edge Detect
13
Oscillator Module
14
Direct Memory Access (DMA) Controller
15
CAN Flexible Data-Rate (FD) Protocol Module
16
High-Resolution PWM with Fine Edge Placement
17
40 MSPS Analog-to-Digital Converter (ADC)
18
Effects of Reset
19
Integrated Touch Controller (ITC)
20
High-Speed Analog Comparator with Slope Compensation DAC
21
Quadrature Encoder Interface (QEI)
22
Universal Asynchronous Receiver Transmitter (UART)
23
Serial Peripheral Interface (SPI)
24
Inter-Integrated Circuit (I
2
C)
25
Single-Edge Nibble Transmission (SENT)
26
Bidirectional Serial Synchronous (BiSS) Module
27
Timers
28
Capture/Compare/PWM/Timer Modules (SCCP/MCCP)
29
Configurable Logic Cell (CLC)
30
Peripheral Trigger Generator (PTG)
31
32-Bit Programmable Cyclic Redundancy Check (CRC) Generator
32
Current Bias Generator (CBG)
33
UREF Reference Output
34
Operational Amplifier (Op Amp)
35
Watchdog Timer (WDT)
36
Deadman Timer (DMT)
37
Device Power-Saving Modes
38
JTAG Interface
39
In-Circuit Debugger
40
Instruction Set Summary
41
Development Support
42
Electrical Characteristics
43
Packaging Information
44
Revision History
45
Product Identification System
Microchip Information
11.10.5 Interrupt Setup Procedures
