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dsPIC33AK512MPS512 Family Data Sheet

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24 Inter-Integrated Circuit (I²C)
24.2 Architectural Overview
24.2.1 Bus Protocol
24.2.1.7 Bus Idle (I)

Operating Conditions
High-Performance dsPIC33A DSP/RISC CPU
Memory Features
Security Features
High-Speed PWM
High-Speed Analog-to-Digital Converters
Peripheral Features
Controller Features
Analog Features
Safety Features
Functional Safety Support
Qualification
Programming and Debug Interfaces
dsPIC33AK512MPS512 Family Features
Pin Diagrams
1 Pinout I/O Descriptions
2 Device Overview
3 Guidelines for Getting Started with Digital Signal Controllers
4 CPU
5 Memory Organization
6 Data Memory
7 Flash Program Memory
8 Configuration Bits
9 Security Module
10 Resets
11 Interrupt Controller
12 I/O Ports with Edge Detect
13 Oscillator Module
14 Direct Memory Access (DMA) Controller
15 CAN Flexible Data-Rate (FD) Protocol Module
16 High-Resolution PWM with Fine Edge Placement
17 40 MSPS Analog-to-Digital Converter (ADC)
18 Effects of Reset
19 Integrated Touch Controller (ITC)
20 High-Speed Analog Comparator with Slope Compensation DAC
21 Quadrature Encoder Interface (QEI)
22 Universal Asynchronous Receiver Transmitter (UART)
23 Serial Peripheral Interface (SPI)
24 Inter-Integrated Circuit (I²C)
25 Single-Edge Nibble Transmission (SENT)
26 Bidirectional Serial Synchronous (BiSS) Module
27 Timers
28 Capture/Compare/PWM/Timer Modules (SCCP/MCCP)
29 Configurable Logic Cell (CLC)
30 Peripheral Trigger Generator (PTG)
31 32-Bit Programmable Cyclic Redundancy Check (CRC) Generator
32 Current Bias Generator (CBG)
33 UREF Reference Output
34 Operational Amplifier (Op Amp)
35 Watchdog Timer (WDT)
36 Deadman Timer (DMT)
37 Device Power-Saving Modes
38 JTAG Interface
39 In-Circuit Debugger
40 Instruction Set Summary
41 Development Support
42 Electrical Characteristics
43 Packaging Information
44 Revision History
45 Product Identification System
Microchip Information

24.2.1.7 Bus Idle (I)

Both data and clock lines remain high after a Stop condition and before a Start condition.

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