24.4.17 I²Cx Bus SDA Set-Up Time Register^{(1),
(2), (3)}

Note:

Timer runs with peripheral clock.
This provides a delay between writing to the transmit buffer and releasing the SCL by hardware; it is used for the release of SCL by hardware.
In Smart mode, the SDA set-up timer is used by hardware to release SCL.

Name:	I2CxSDASUT
Offset:	0x18C0, 0x1910, 0x1960


Bit	31	30	29	28	27	26	25	24
	SDASUTEN
Access	R/W
Reset	0


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
	SDASUT[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	SDASUT[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 31 – SDASUTEN I²C Bus SDA-to-SCL Set-up Time Enable bit

Bits 15:0 – SDASUT[15:0] I²C Bus SDA-to-SCL Set-up Time Timer bits