4.4.1 Architectural Overview
The PBU is a direct-mapped 128-line cache that helps in providing faster program data fetches to the CPU from Flash memory. The PBU provides program data from an internal instruction buffer, but if it is not available in the internal buffer, the PBU may fetch program data from Flash. Flash fetch operations are, therefore, accelerated when data are sourced from internal PBU buffers.
The PBU provides an interface between the Program Flash Memory (PFM) and the CPU instruction bus and has the following components associated for operation.
- Instruction Stream Buffer (ISB) - Also termed as the Prefetch Unit (PFU), it is available for prefetching and caching linear PFM instruction flows. ISB is the component that buffers program data words from the program memory. The ISB consists of one or more buffers of a fixed depth. Each buffer holds one or more lines of data fetches from Flash memory. The data held in each buffer represents a linear code flow. These are defined as internal PBU buffers.
- Instruction Cache (IC) - Used for caching the target instructions that are most frequently hit. The IC refers to both the cache memory and the associated control logic that form the cache. The PBU contains a direct-mapped 128-line cache. The required width for the cache is 129-bits, with the extra bit being required for parity.
- Integrity Checking Logic - Provides parity checks on program data stored in the IC to ensure data integrity. This logic provides parity checking and fault injection on the contents of RAM associated with the IC.
The PBU assumes Flash data width and Flash access speed are sufficient to allow linear program execution at the required speed using only the ISB. The ISB serves as the prefetch buffer and allows the next line of Flash to be fetched as instructions from the current line are executed.
The Instruction Cache (IC) becomes useful when there are frequent program flow changes in the source code. A program flow change will result in extra clock cycles because the current Flash fetch must be allowed to complete and then a new fetch must be initiated at the new location. If the desired program data is available in the IC, the data may be sourced immediately without waiting for the ISB to complete a new fetch from Flash. However, PBU uses a larger, direct-mapped instruction cache and has little control and status interface available to the user as its operations are transparent.