BMX Bus Error During Row Programming

If the NVMSRCADR value is invalid, and the NVM is performing a row programming operation, the BMX will not be able to connect to the RAM containing the needed data. The BMX will generate an error if it cannot access the address specified by the NVMSRCADR register. This error triggers the NVM to terminate the row programming operation and set the WRERR and the URERR status bits. The NVM Module will generate a NVM Trap signal to the interrupt controller to alert the user software that a bus error has occurred.