7.3.3 Error Correcting Code (ECC)

To improve program memory performance and durability, select dsPIC33A devices that include Error Correcting Code (ECC) functionality as an integral part of the Flash memory controller. ECC can determine the presence of single-bit errors in program data, including which bit is in error, and correct the data without user intervention. When implemented, ECC is automatic and cannot be disabled.

Additionally, users can inject single-bit errors or double-bit errors into the ECC calculation. This allows functional safety focused users to be able to test the ECC calculation and Fault generation logic at run time to verify there are no latent Faults present in the system.

When data are written to program memory, ECC generates a 9-bit Hamming code parity value, 8-bit Single Error Correction (SEC) value and one extra bit to support Double Error Correction (DED) for every 128-bit input data value. Parity data are not memory-mapped and are inaccessible. When the data are read back, the ECC calculates parity on them and compares them to the previously stored parity value. If a parity mismatch occurs, there are two possible outcomes:

The user controls the ECC Fault injection through the ECCCON (NVMECCCON), ECCFPTR (NVMECCFPTR ), ECCFADDR (NVMECCFADDR) and the ECCSTAT (NVMECCSTAT) SFRs. In keeping with all other NVM Controller SFRs, writes to these registers are inhibited during any Flash write sequence. Users may either create intentional Faults in data read from the Flash or in data written into the Flash. Single-bit or double-bit Faults may be injected into any location within the data word (i.e., any data bit but also including the ECC parity bits).