16.5.2.6.10 PCI Source Synchronized to EOC, Latched Modes

When the PCI acceptance logic is operated in the Latched mode and PSYNC = 1, the PCI source is synchronized to the EOC event, as shown in Figure 16-27. The synchronization logic delays the rising edge of the PCI source signal until the next occurrence of the EOC signal. The output of the synchronization logic is deasserted on the falling edge of the PCI source signal. The output of the synchronization logic is then used to set the SR latch. A PCI input pulse that operates entirely within one EOC period will not assert the PCI active signal. This is because the falling edge of the PCI input signal resets the EOC synchronization logic before an event can be produced.