16.5.2.6.3 PCI Output Control Priority

If multiple PCI output control blocks are enabled to control the same set of PWM output pins, there may be conflicts due to the output state values programmed into the FLT1DAT[1:0], FLT2DAT[1:0], CLDAT[1:0] and FFDAT[1:0] control bits. The following priority order is used to determine which source has control of the PWM output pins:

  1. Debugger Halt Event
  2. PCI Fault 1 Event
  3. PCI Fault 2 Event
  4. Software Override Event
  5. PCI Current-Limit Event
  6. PCI Feed-Forward Event
  7. PWM Generator

    The PWM generator has the lowest (default) priority. A halt of the CPU execution due to a debugger operation has the highest priority. Feed-forward events typically (but not always) drive the PWM pins to an active state, so the PCI Feed-Forward function is given a lower priority than a software override of the pins.