17.4.7 Interrupts

Each channel has an individual result ready interrupt with a ADnCHxIF flag in the corresponding IFS register. The channel interrupt can be enabled by setting the ADnCHxIE bit in the IEC register. There are two interrupt modes defined by the IRQSEL bit (ADnCHxCON1[21]). If the IRQSEL bit is zero, the channel interrupt is generated after each single conversion when the result is ready in the ADnCHxRES register. If the IRQSEL bit is set, the channel interrupt is generated when data are ready in the ADnCHxDATA register. For the IRQSEL bit = 1 option, the channel interrupt is generated:

After each conversion for the Single Conversion mode (MODE[1:0] bits = ‘00’).
For the Window mode (MODE[1:0] bits = `01`), when the number of conversions reaches a value in CNTx[15:0] bits (ADnCHxCNT[15:0]) or when the gate signal defined by TRG1SRC[5:0] bits is deasserted.
When all conversions are finished for the Oversampling or Integration modes (MODE[1:0] bits = ‘10’ or ‘11’).

The result-ready interrupt can be generated before the result is available in the ADnCHxDATA register. This feature is called “Early Interrupt” and can reduce the ADC channel interrupt latency. This early interrupt for the channel is enabled by the setting of the EIEN bit (ADnCHxCON1[22]). Early interrupts can only be used in Single Conversion mode (MODE[1:0] bits = ‘00’). When the early interrupt is enabled (EIEN bit = ‘1’), the channel individual interrupt is generated, and the CHxRDY bit in the ADnSTAT register is set at the start of the sampling time. The software must guarantee that the channel data are ready when the ADnCHxDATA register is read in the interrupt service routine. Each channel also has a comparator interrupt with an ADnCMPxIF flag in the corresponding IFS register. The channel comparator interrupt is generated upon a set number of criteria match events as defined by the ADCMPCNT[9:0] and CMPMODE bits (see Comparator for details). The comparator interrupt is enabled by setting the ADnCMPxIE bit in the IEC register.