3.4 Buck Converter Guidelines and Considerations

The dsPIC® uses a synchronous buck converter to step down VDD in order to supply the core in an efficient manner. The buck's pin considerations are as follows:

  • SWVDD – This power pin is the positive input to the buck converter. This pin has high transient currents and should have a low impedance path to VDD. A 10 µF (4.7 µF minimum) capacitor is recommended in conjunction with a 0.1 µF capacitor as close as possible to the pin.
  • SWVSS – This power pin is the negative input to the buck converter. This pin has high transient currents and should have a low-impedance path to the PCB ground.
  • LX – This pin is the buck's switching node and should be connected as the input to the inductor. This pin is sensitive to parasitics and should be handled accordingly.
  • VDDCORE – This pin is the input into the core and must be connected as the output of the inductor. The buck's 10 µF output capacitor must be placed on this pin in conjunction with a 0.1 µF decoupling capacitor as close to the pin as possible.

The buck converter maintains a constant voltage on VDDCORE by adjusting its duty cycle to compensate for transient conditions. Figure 3-1 illustrates a simplified schematic of the portion of the buck internal to the dsPIC®.

Figure 3-1. Buck Regulator Topology

No other connections should be made to the VDDCORE or LX pins. The output voltage of the buck converter is listed in Electrical Characteristics. An example application circuit is shown in Figure 3-2.

Figure 3-2. Example Application Circuit