3.1 Libero Configurators

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The transceiver configurator is the preferred tool for the wrapper generation needed to instantiate the transceiver primitive macros called PF_XCVR_REF_CLK, PF_TXPLL, and PF_PCIE. The configurator is part of the Libero SoC design tools and is available when the macros are downloaded into the Libero catalog. This section describes how to enter the configuration parameters in the Libero configurator GUIs. The following table provides details of three Libero configurator modules used by the Libero FPGA design when the blocks are implemented in the design. These three blocks must be instantiated and configured in the PCIe design.

Table 3-1. Libero Configurators in Libero Software
Libero Configurator	Macro	Details
Transceiver Reference Clock	PF_XCVR_REF_CLK	Generates the reference clock based on the input to the GUI—differential or single-ended input buffer and single or dual-clock input to the transmit PLL clock network. Reference clocks for PCIESS systems use differential HCSL/LVDS. However, this can vary according to the system application.
Transmit PLL¹	PF_TXPLL	Generates the TxPLL/TxPLL_SSC based on the input to the GUI. Typically, a 100 MHz clock (Refclk) with greater than ±300 ppm frequency stability is used for PCIe applications. For Refclk flexibility, the PCIESS block accepts 100 MHz, 125 MHz, or 156.25 MHz input and translates for PCIe Gen1 or Gen2 speeds.
PCI Express	PF_PCIE	Configures the requested number of lanes with the same PMA and PCS settings—location of each lane and CDRPLL settings. The configurator has presets for all the supported protocols.
⁽¹⁾ It is not advisable to share the TxPLL with other serial protocols that have a tight transmit jitter specification.

Each transceiver module configurator guides the user through a sequential selection of choices and defaults. Each configurator maintains a macro diagram that displays module ports based on the current configuration. When all of the choices are made, the configurator generates a macro specific to the requirements of the design. Only the relevant ports appear in the generated macro.

A PCIe design requires the transceiver reference clock and transceivers transmit PLL blocks to be configured and instantiated in the design.

For more information on TX_REF_CLK and TX_PLL block configurators, see PolarFire Family Transceiver User Guide.

For information about how to debug PCIe, see SmartDebug User Guide.