3.3 Design Constraints

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No physical design constraints (PDC) are required for PCIe. Constraints are required for PF_TXPLL and PF_XCVR_REF_CLK. The Libero software automatically places the PCIESS blocks. The PCIESS overlays the related transceiver quad 0 lanes. Therefore, when only PCIe 0 is used, it can be used as a x1 or x2 link.

Timing constraints are automatically generated by Libero SoC.

Note: Do not add user-supplied clock constraint if the paths are internal to the core.

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