3 Pin Allocation Tables

Table 3-1. 28-Pin Allocation Table
I/O⁽²⁾	28- Pin SPDIP, SOIC, SSOP	28- Pin VQFN	A/D	Reference	Operational Amplifier	Comparator	ZCD/Analog Peripheral Manager	Timers	16-Bit PWM/ CCP	CWG	CLC	SPI	I²C	UART	IOC	Interrupt	Basic
RA0	2	27	ANA0	—	OPA1OR⁽¹⁾	C1IN0- C2IN0-	—	—	—	—	CLCIN0⁽¹⁾ CLCIN4⁽¹⁾	—	—	—	IOCA0	—	—
RA1	3	28	ANA1⁽⁶⁾	—	OPA1OUT OPA2IN1- OPA2IN1+	C1IN1- C2IN1-	—	—	—	—	CLCIN1⁽¹⁾ CLCIN5⁽¹⁾	—	—	—	IOCA1	—	—
RA2	4	1	ANA2	DAC1OUT1 DAC2OUT1 DAC3OUT1 V_REF- (DAC1) V_REF- (ADC)	OPA1IN0- OPA1IN0+	C1IN0+ C2IN0+	—	—	—	—	—	—	—	—	IOCA2	—	—
RA3	5	2	ANA3⁽⁶⁾	V_REF+ (DAC1) V_REF+ (ADC)	—	C1IN1+	—	—	—	—	—	—	—	—	IOCA3	—	—
RA4	6	3	ANA4	—	OPA1IN1- OPA1IN1+	—	—	T0CKI⁽¹⁾	—	—	—	—	—	—	IOCA4	—	—
RA5	7	4	ANA5⁽⁶⁾	—	OPA1IN2- OPA1IN2+	—	—	—	—	—	—	SS1⁽¹⁾	—	—	IOCA5	—	—
RA6	10	7	ANA6⁽⁶⁾	—	—	—	—	—	—	—	—	—	—	—	IOCA6	—	CLKOUT OSC2
RA7	9	6	ANA7⁽⁶⁾	—	—	—	—	—	—	—	—	—	—	—	IOCA7	—	OSC1 CLKIN
RB0	21	18	ANB0⁽⁶⁾	V_REF+ (DAC2)	—	C2IN1+	ZCDIN	—	—	CWG1⁽¹⁾	—	—	—	—	IOCB0	INT0⁽¹⁾	—
RB1	22	19	ANB1	—	OPA2OUT OPA1IN3- OPA1IN3+	C1IN3- C2IN3-	—	—	—	—	—	—	—⁽⁴⁾	—	IOCB1	INT1⁽¹⁾	—
RB2	23	20	ANB2⁽⁶⁾	—	OPA2IN3- OPA2IN3+	—	—	—	—	—	—	—	—⁽⁴⁾	—	IOCB2	INT2⁽¹⁾	—
RB3	24	21	ANB3	—	OPA2IN2- OPA2IN2+	C1IN2- C2IN2-	—	—	—	—	—	—	—	—	IOCB3	—	—
RB4	25	22	ANB4⁽⁶⁾ ADACT⁽¹⁾	—	OPA2IN0- OPA2IN0+	—	—	—	—	—	—	—	—	—	IOCB4	—	—
RB5	26	23	ANB5	V_REF- (DAC2)	—	—	—	T1G⁽¹⁾ TUIN1⁽¹⁾	—	—	—	—	—	—	IOCB5	—	—
RB6	27	24	ANB6⁽⁶⁾	—	—	—	—	—	—	—	CLCIN2⁽¹⁾ CLCIN6⁽¹⁾	—	—	CTS2⁽¹⁾	IOCB6	—	ICSPCLK
RB7	28	25	ANB7	DAC1OUT2 DAC2OUT2 DAC3OUT2	—	—	—	—	PWM3ERS⁽¹⁾	—	CLCIN3⁽¹⁾ CLCIN7⁽¹⁾	—	—	RX2⁽¹⁾	IOCB7	—	ICSPDAT
RC0	11	8	ANC0	—	—	—	—	T1CKI⁽¹⁾ T3CKI⁽¹⁾ T3G⁽¹⁾ TUIN0⁽¹⁾	—	—	—	—	—	—	IOCC0	—	SOSCO
RC1	12	9	ANC1⁽⁶⁾	—	—	—	—	—	CCP2⁽¹⁾	—	—	—	—	—	IOCC1	—	SOSCI
RC2	13	10	ANC2	V_REF+ (DAC3)	—	—	—	—	PWMIN0⁽¹⁾ CCP1⁽¹⁾	—	—	—	—	—	IOCC2	—	—
RC3	14	11	ANC3⁽⁶⁾	—	—	—	—	T2IN⁽¹⁾	PWM1ERS⁽¹⁾	—	—	SCK1⁽¹⁾	SCL1^(3,4)	—	IOCC3	—	—
RC4	15	12	ANC4	—	—	—	APMCLK	—	—	—	—	SDI1⁽¹⁾	SDA^(3,4)	—	IOCC4	—	—
RC5	16	13	ANC5	V_REF- (DAC3)	—	—	—	T4IN⁽¹⁾	PWM2ERS⁽¹⁾	—	—	—	—	—	IOCC5	—	—
RC6	17	14	ANC6⁽⁶⁾	—	OPA2OR⁽¹⁾	—	—	—	PWMIN1⁽¹⁾	—	—	—	—	CTS1⁽¹⁾	IOCC6	—	—
RC7	18	15	ANC7	—	—	—	—	—	—	—	—	—	—	RX1⁽¹⁾	IOCC7	—	—
RE3	1	26	—	—	—	—	—	—	—	—	—	—	—	—	IOCE3	—	V_PP/MCLR
V_SS	19	16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	V_SS
V_DD⁽⁵⁾	20	17	—	—	—	—	—	—	—	—	—	—	—	—	—	—	V_DD⁽⁵⁾
V_SS	8	5	—	—	—	—	—	—	—	—	—	—	—	—	—	—	V_SS
OUT⁽²⁾	—	—	ADGRDA ADGRDB	—	—	C1OUT C2OUT	—	TMR0	PWM11 PWM12 PWM21 PWM22 PWM31 PWM32 CCP1 CCP2	CWG1A CWG1B CWG1C CWG1D	CLC1OUT CLC2OUT CLC3OUT CLC4OUT CLC5OUT CLC6OUT CLC7OUT CLC8OUT	SS1 SCK1 SDO1	SDA1 SCL1	DTR1 RTS1 TX1 DTR2 RTS2 TX2	—	—	—
Note: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to the peripheral input selection table for details on which PORT pins may be used for this signal. All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options as described in the peripheral output selection table. This is a bidirectional signal. For normal module operation, the firmware may map this signal to the same pin in both the PPS input and PPS output registers. These pins are configured for I²C logic levels; The SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RB1) will operate, but input logic levels will be standard LVBUF/ST as selected by the INLVL register, instead of the I²C specific or SMBus input buffer thresholds. A 0.1 μF bypass capacitor to V_SS is required on the V_DD pin. This pin can be used as either a positive or negative analog input channel to the ADC.