48.7.8 PWM Interrupt Status Register 1
Note: Reading PWM_ISR1 automatically clears CHIDx and FCHIDx flags.
| Name: | PWM_ISR1 |
| Offset: | 0x1C |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| FCHID2 | FCHID1 | FCHID0 | |||||||
| Access | R | R | R | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CHID2 | CHID1 | CHID0 | |||||||
| Access | R | R | R | ||||||
| Reset | 0 | 0 | 0 |
Bits 16, 17, 18 – FCHIDx Fault Protection Trigger on Channel x
| Value | Description |
|---|---|
| 0 | No new trigger of the fault protection since the last read of PWM_ISR1. |
| 1 | At least one trigger of the fault protection since the last read of PWM_ISR1. |
Bits 0, 1, 2 – CHIDx Counter Event on Channel x
| Value | Description |
|---|---|
| 0 | No new counter event has occurred since the last read of PWM_ISR1. |
| 1 | At least one counter event has occurred since the last read of PWM_ISR1. |