48.7.7 PWM Interrupt Mask Register 1

Name:	PWM_IMR1
Offset:	0x18
Reset:	0x00000000
Property:	Read-only


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
						FCHID2	FCHID1	FCHID0
Access						R	R	R
Reset						0	0	0


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
						CHID2	CHID1	CHID0
Access						R	R	R
Reset						0	0	0

Bits 16, 17, 18 – FCHIDx Fault Protection Trigger on Channel x Interrupt Mask

Bits 0, 1, 2 – CHIDx Counter Event on Channel x Interrupt Mask

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