48.7.6 PWM Interrupt Disable Register 1

This register can only be written if bits WPSWS1 and WPHWS1 are cleared in the PWM Write Protection Status Register.

Name:	PWM_IDR1
Offset:	0x14
Reset:	–
Property:	Write-only


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
						FCHID2	FCHID1	FCHID0
Access						W	W	W
Reset						–	–	–


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
						CHID2	CHID1	CHID0
Access						W	W	W
Reset						–	–	–

Bits 16, 17, 18 – FCHIDx Fault Protection Trigger on Channel x Interrupt Disable

Bits 0, 1, 2 – CHIDx Counter Event on Channel x Interrupt Disable

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