48.7.16 PWM Interrupt Status Register 2
Reading PWM_ISR2 automatically clears flags WRDY, UNRE and CMPSx.
| Name: | PWM_ISR2 |
| Offset: | 0x40 |
| Reset: | 0x00000006 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CMPU7 | CMPU6 | CMPU5 | CMPU4 | CMPU3 | CMPU2 | CMPU1 | CMPU0 | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CMPM7 | CMPM6 | CMPM5 | CMPM4 | CMPM3 | CMPM2 | CMPM1 | CMPM0 | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| UNRE | TXBUFE | ENDTX | WRDY | ||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 1 | 1 | 0 |
Bits 16, 17, 18, 19, 20, 21, 22, 23 – CMPUx Comparison x Update
| Value | Description |
|---|---|
| 0 |
The comparison x has not been updated since the last read of the PWM_ISR2 register. |
| 1 |
The comparison x has been updated at least one time since the last read of the PWM_ISR2 register. |
Bits 8, 9, 10, 11, 12, 13, 14, 15 – CMPMx Comparison x Match
| Value | Description |
|---|---|
| 0 |
The comparison x has not matched since the last read of the PWM_ISR2 register. |
| 1 |
The comparison x has matched at least one time since the last read of the PWM_ISR2 register. |
Bit 3 – UNRE Synchronous Channels Update Underrun Error
| Value | Description |
|---|---|
| 0 |
No Synchronous Channels Update Underrun has occurred since the last read of the PWM_ISR2 register. |
| 1 |
At least one Synchronous Channels Update Underrun has occurred since the last read of the PWM_ISR2 register. |
Bit 2 – TXBUFE PDC TX Buffer Empty
| Value | Description |
|---|---|
| 0 |
PWM_TCR or PWM_TCNR has a value other than 0. |
| 1 |
Both PWM_TCR and PWM_TCNR have a value other than 0. |
Bit 1 – ENDTX PDC End of TX Buffer
| Value | Description |
|---|---|
| 0 |
The Transmit Counter register has not reached 0 since the last write of the PDC. |
| 1 |
The Transmit Counter register has reached 0 since the last write of the PDC. |
Bit 0 – WRDY Write Ready for Synchronous Channels Update
| Value | Description |
|---|---|
| 0 |
New duty-cycle and dead-time values for the synchronous channels cannot be written. |
| 1 |
New duty-cycle and dead-time values for the synchronous channels can be written. |