48.7.21 PWM Output Selection Set Update Register
| Name: | PWM_OSSUPD |
| Offset: | 0x54 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| OSSUPL2 | OSSUPL1 | OSSUPL0 | |||||||
| Access | W | W | W | ||||||
| Reset | – | – | – |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| OSSUPH2 | OSSUPH1 | OSSUPH0 | |||||||
| Access | W | W | W | ||||||
| Reset | – | – | – |
Bits 16, 17, 18 – OSSUPLx Output Selection Set for PWML output of the channel x
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Output override value OOVLx selected as PWML output of channel x at the beginning of the next channel x PWM period. |
Bits 0, 1, 2 – OSSUPHx Output Selection Set for PWMH output of the channel x
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Output override value OOVHx selected as PWMH output of channel x at the beginning of the next channel x PWM period. |