15.4.6.1 VDD3V3 Supply Monitor Reset

The VDD3V3 supply monitor can be configured to generate a reset of the VDDCORE domain This is enabled by setting the SUPC_SMMR.VDD3V3SMRSTEN=1.

If SUPC_SMMR.VDD3V3SMRSTEN=1 and a VDD3V3 supply monitor event occurs, the VDDCORE source reset signal is immediately activated for a minimum of one slow clock cycle.

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