35.7.5 QSPI Interrupt Status Register
| Name: | QSPI_ISR |
| Offset: | 0x10 |
| Reset: | 0x000000F0 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TOUT | |||||||||
| Access | R | ||||||||
| Reset | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CSRA | CSFA | QITR | QITF | LWRA | INSTRE | CSR | |||
| Access | R | R | R | R | R | R | R | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TXBUFE | RXBUFF | ENDTX | ENDRX | OVRES | TXEMPTY | TDRE | RDRF | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 |
Bit 17 – TOUT QSPI Time-out
| Value | Description |
|---|---|
| 0 | No QSPI time-out occurred since the last write of RTOUT bit on QSPI_CR. |
| 1 | At least one QSPI time-out occurred since the last write of RTOUT bit on QSPI_CR. |
Bit 15 – CSRA Chip Select Rise Autoclear
| Value | Description |
|---|---|
| 0 | No chip select rise has been detected since beginning of the last command or the last read of QSPI_ISR. |
| 1 | One chip select rise has been detected since the beginning of the last command or the last read of QSPI_ISR. |
Bit 14 – CSFA Chip Select Fall Autoclear
| Value | Description |
|---|---|
| 0 | No chip select fall has been detected since end of the last command or the last read of QSPI_ISR. |
| 1 | One chip select fall has been detected since the end of the last command or the last read of QSPI_ISR. |
Bit 13 – QITR QSPI Interrupt Rise
| Value | Description |
|---|---|
| 0 | No rising of the QSPI memory interrupt line has been detected since the last read of QSPI_ISR. |
| 1 | At least one QSPI memory interrupt line rising edge occurred since the last read of QSPI_ISR. |
Bit 12 – QITF QSPI Interrupt Fall
| Value | Description |
|---|---|
| 0 | No falling of the QSPI memory interrupt line has been detected since the last read of QSPI_ISR. |
| 1 | At least one QSPI memory interrupt line falling edge occurred since the last read of QSPI_ISR. |
Bit 11 – LWRA Last Write Access (cleared on read)
| Value | Description |
|---|---|
| 0 | Last write access has not been sent since the last read of QSPI_SR or NBWRA = 0. |
| 1 | At least one last write access has been sent since the last read of QSPI_SR. |
Bit 10 – INSTRE Instruction End Status (cleared on read)
| Value | Description |
|---|---|
| 0 | No instruction end has been detected since the last read of QSPI_SR. |
| 1 | At least one instruction end has been detected since the last read of QSPI_SR. |
Bit 8 – CSR Chip Select Rise (cleared on read)
| Value | Description |
|---|---|
| 0 | No chip select rise has been detected since the last read of QSPI_SR. |
| 1 | At least one chip select rise has been detected since the last read of QSPI_SR. |
Bit 7 – TXBUFE TX Buffer Empty
| Value | Description |
|---|---|
| 0 |
QSPI_TCR or QSPI_TNCR has a value other than 0. |
| 1 |
Both QSPI_TCR and QSPI_TNCR have a value of 0. |
Bit 6 – RXBUFF RX Buffer Full
| Value | Description |
|---|---|
| 0 |
QSPI_RCR or QSPI_RNCR has a value other than 0. |
| 1 |
Both QSPI_RCR and QSPI_RNCR have a value of 0. |
Bit 5 – ENDTX End of TX Buffer
| Value | Description |
|---|---|
| 0 |
The Receive Counter register has not reached 0 since the last write in QSPI_TCR or QSPI_TNCR. |
| 1 |
The Receive Counter register has reached 0 since the last write in QSPI_TCR or QSPI_TNCR. |
Bit 4 – ENDRX End of RX Buffer
| Value | Description |
|---|---|
| 0 |
The Receive Counter register has not reached 0 since the last write in QSPI_RCR or QSPI_RNCR. |
| 1 |
The Receive Counter register has reached 0 since the last write in QSPI_RCR or QSPI_RNCR. |
Bit 3 – OVRES Overrun Error Status (cleared on read)
An overrun occurs when QSPI_RDR is loaded at least twice from the serializer since the last read of the QSPI_RDR.
| Value | Description |
|---|---|
| 0 |
No overrun has been detected since the last read of QSPI_ISR. |
| 1 |
At least one overrun error has occurred since the last read of QSPI_ISR. |
Bit 2 – TXEMPTY Transmission Registers Empty (cleared by writing QSPI_TDR)
| Value | Description |
|---|---|
| 0 | As soon as data is written in QSPI_TDR. |
| 1 | QSPI_TDR and the internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion of such delay. |
Bit 1 – TDRE Transmit Data Register Empty (cleared by writing QSPI_TDR)
TDRE equals zero when the QSPI is disabled or at reset. The QSPI enable command sets this bit to one.
| Value | Description |
|---|---|
| 0 | Data has been written to QSPI_TDR and not yet transferred to the serializer. |
| 1 | The last data written in the QSPI_TDR has been transferred to the serializer. |
Bit 0 – RDRF Receive Data Register Full (cleared by reading QSPI_RDR)
| Value | Description |
|---|---|
| 0 | No data has been received since the last read of QSPI_RDR. |
| 1 | Data has been received and the received data has been transferred from the serializer to QSPI_RDR since the last read of QSPI_RDR. |